From c660ea87be711f6b8f9e1c6c6c63ecf62275e520 Mon Sep 17 00:00:00 2001 From: David Banks Date: Fri, 20 Sep 2019 15:34:44 +0100 Subject: [PATCH] Updated lx9_dave/ice6502 for active level shifter design Change-Id: Ib2e98050d02c9c1e3dd7c9a9b63eea118b95a540 --- src/W65C02CpuMon.vhd | 62 ++++++++++++++++-------------- target/lx9_dave/ice6502/board.ucf | 63 +++++++++++++++++++------------ 2 files changed, 72 insertions(+), 53 deletions(-) diff --git a/src/W65C02CpuMon.vhd b/src/W65C02CpuMon.vhd index 23319eb..0a2c00c 100644 --- a/src/W65C02CpuMon.vhd +++ b/src/W65C02CpuMon.vhd @@ -1,5 +1,5 @@ -------------------------------------------------------------------------------- --- Copyright (c) 2018 David Banks +-- Copyright (c) 2019 David Banks -- -------------------------------------------------------------------------------- -- ____ ____ @@ -8,11 +8,11 @@ -- \ \ \/ -- \ \ -- / / Filename : W65C02CpuMon.vhd --- /___/ /\ Timestamp : 20/11/2018 +-- /___/ /\ Timestamp : 20/09/2019 -- \ \ / \ -- \___\/\___\ -- ---Design Name: W65C02BusMon +--Design Name: W65C02CpuMon --Device: XC6SLX9 -- -- @@ -20,6 +20,7 @@ -- OEAH_n -- OEAL_n -- OED_n +-- DIRD -- BE -- ML_n -- VP_n @@ -31,28 +32,28 @@ use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity W65C02CpuMon is - generic ( + generic ( UseT65Core : boolean := true; UseAlanDCore : boolean := false; LEDsActiveHigh : boolean := true; -- default value for EEPIZZA - SW1ActiveHigh : boolean := true; -- default value for EEPIZZA - SW2ActiveHigh : boolean := true; -- default value for EEPIZZA - ClkMult : integer := 10; -- default value for EEPIZZA - ClkDiv : integer := 31; -- default value for EEPIZZA - ClkPer : real := 20.000 -- default value for EEPIZZA + SW1ActiveHigh : boolean := false; -- default value for EEPIZZA + SW2ActiveHigh : boolean := false; -- default value for EEPIZZA + ClkMult : integer := 8; -- default value for EEPIZZA + ClkDiv : integer := 25; -- default value for EEPIZZA + ClkPer : real := 16.000 -- default value for EEPIZZA ); port ( - clock49 : in std_logic; + clock : in std_logic; -- 6502 Signals - Phi0 : in std_logic; - Phi1 : out std_logic; - Phi2 : out std_logic; + PhiIn : in std_logic; + Phi1Out : out std_logic; + Phi2Out : out std_logic; IRQ_n : in std_logic; NMI_n : in std_logic; Sync : out std_logic; Addr : out std_logic_vector(15 downto 0); - R_W_n : out std_logic; + R_W_n : out std_logic_vector(1 downto 0); Data : inout std_logic_vector(7 downto 0); SO_n : in std_logic; Res_n : inout std_logic; @@ -64,15 +65,18 @@ entity W65C02CpuMon is VP_n : out std_logic; -- Level Shifter Controls + OERW_n : out std_logic; OEAH_n : out std_logic; OEAL_n : out std_logic; OED_n : out std_logic; + DIRD : out std_logic; -- External trigger inputs trig : in std_logic_vector(1 downto 0); - -- Jumpers - fakeTube_n : in std_logic; + -- ID/mode inputs + mode : in std_logic; + id : in std_logic_vector(3 downto 0); -- Serial Console avr_RxD : in std_logic; @@ -83,9 +87,9 @@ entity W65C02CpuMon is sw2 : in std_logic; -- LEDs + led1 : out std_logic; + led2 : out std_logic; led3 : out std_logic; - led6 : out std_logic; - led8 : out std_logic; -- OHO_DY1 LED display tmosi : out std_logic; @@ -112,12 +116,12 @@ begin ClkPer => ClkPer ) port map ( - clock49 => clock49, + clock49 => clock, -- 6502 Signals - Phi0 => Phi0, - Phi1 => Phi1, - Phi2 => Phi2, + Phi0 => PhiIn, + Phi1 => Phi1Out, + Phi2 => Phi2Out, IRQ_n => IRQ_n, NMI_n => NMI_n, Sync => Sync, @@ -132,7 +136,7 @@ begin trig => trig, -- Jumpers - fakeTube_n => fakeTube_n, + fakeTube_n => '1', -- Serial Console avr_RxD => avr_RxD, @@ -143,9 +147,9 @@ begin sw2 => sw2, -- LEDs - led3 => led3, - led6 => led6, - led8 => led8, + led3 => led2, -- trig 0 + led6 => led3, -- trig 1 + led8 => led1, -- break -- OHO_DY1 LED display tmosi => tmosi, @@ -154,15 +158,17 @@ begin ); -- 6502 Outputs - R_W_n <= R_W_n_int; + R_W_n <= R_W_n_int & R_W_n_int; -- 65C02 Outputs ML_n <= '1'; VP_n <= '1'; -- Level Shifter Controls + OERW_n <= not (BE); OEAH_n <= not (BE); OEAL_n <= not (BE); - OED_n <= not (BE or (Phi0 and not R_W_n_int)); -- TODO: might need to use a slightly delayed version of Phi0 here + OED_n <= not (BE and PhiIn); -- TODO: might need to use a slightly delayed version of Phi2 here + DIRD <= R_W_n_int; end behavioral; diff --git a/target/lx9_dave/ice6502/board.ucf b/target/lx9_dave/ice6502/board.ucf index 0516563..7202083 100644 --- a/target/lx9_dave/ice6502/board.ucf +++ b/target/lx9_dave/ice6502/board.ucf @@ -1,16 +1,16 @@ -NET "clock49" TNM_NET = clk_period_grp_49; -TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.00ns HIGH; +NET "clock" TNM_NET = clk_period_grp_50; +TIMESPEC TS_clk_period_50 = PERIOD "clk_period_grp_50" 20.00ns HIGH; -NET "Phi0" TNM_NET = clk_period_grp_phi0; -TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 250ns LOW; +NET "PhiIn" TNM_NET = clk_period_grp_phi; +TIMESPEC TS_clk_period_phi = PERIOD "clk_period_grp_phi" 250ns LOW; -NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE; +NET "PhiIn" CLOCK_DEDICATED_ROUTE = FALSE; -NET "clock49" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator +NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator NET "VP_n" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1 #NET "Rdy" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2 -NET "Phi1" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3 +NET "Phi1Out" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3 NET "IRQ_n" LOC="P81" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4 NET "ML_n" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5 NET "NMI_n" LOC="P82" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 6 @@ -42,41 +42,54 @@ NET "Data<3>" LOC="P97" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # NET "Data<2>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 31 NET "Data<1>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32 NET "Data<0>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 33 -NET "R_W_n" LOC="P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34 +NET "R_W_n<0>" LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34 +NET "R_W_n<1>" LOC="P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34 #NET "NC" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 35 NET "BE" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 36 -NET "Phi0" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37 +NET "PhiIn" LOC="P80" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37 NET "SO_n" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 38 -NET "Phi2" LOC="P80" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39 +NET "Phi2Out" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39 NET "Res_n" LOC="P74" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 40 -# Level-shifter OE signals -NET "OEAL_n" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +# Output Enables +NET "OERW_n" LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "OEAH_n" LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "OEAL_n" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "OED_n" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "DIRD" LOC="P93" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # LEDs and Switches -NET "led3" LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active -NET "led6" LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active -NET "led8" LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint -NET "sw1" LOC="P132" | IOSTANDARD = LVCMOS33 ; # reset -NET "sw2" LOC="P131" | IOSTANDARD = LVCMOS33 ; # interrupt +NET "led1" LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint +NET "led2" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active +NET "led3" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active +NET "sw1" LOC="P45" | IOSTANDARD = LVCMOS33 ; # reset +NET "sw2" LOC="P66" | IOSTANDARD = LVCMOS33 ; # interrupt -# 7-segment LED -NET tmosi LOC="P45" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET tcclk LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +# ID/Jumper +NET "mode" LOC="P140" | IOSTANDARD = LVCMOS33 ; # mode jumper +NET "id<0>" LOC="P88 " | IOSTANDARD = LVCMOS33 ; # id links +NET "id<1>" LOC="P87 " | IOSTANDARD = LVCMOS33 ; # id links +NET "id<2>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # id links +NET "id<3>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # id links # UART NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ; # External trigger inputs -NET "trig<0>" LOC="P126" | IOSTANDARD = LVCMOS33 ; -NET "trig<1>" LOC="P127" | IOSTANDARD = LVCMOS33 ; +NET "trig<0>" LOC="P127" | IOSTANDARD = LVCMOS33 ; +NET "trig<1>" LOC="P126" | IOSTANDARD = LVCMOS33 ; -# Jumpers -NET "fakeTube_n" LOC="P123" | IOSTANDARD = LVCMOS33 ; +# 7-segment LED (connect to J5 on FPGA board) +NET "tmosi" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "tdin" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "tcclk" LOC="P62" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; + +# Test outputs (connect to J5 on FPGA board) +#NET "test1" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +#NET "test2" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +#NET "test3" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +#NET "test4" LOC="P59" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;