Z80: indicate NMI and INT cycles when single stepping

Change-Id: Iafef4059bd136dd9f3aebf2b03ab5ac186e035a6
This commit is contained in:
David Banks 2019-10-29 15:48:43 +00:00
parent 4818f026b2
commit c6bc245b3d
9 changed files with 32 additions and 12 deletions

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@ -1333,6 +1333,7 @@ void doCmdContinue(char *params) {
}
void initialize() {
PDC_DDR = 0;
CTRL_DDR = 255;
STATUS_DDR = MUXSEL_MASK;
MUX_DDR = 0;

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@ -46,6 +46,7 @@ void doCmdHelp(char *params);
void doCmdIO(char *params);
void doCmdList(char *params);
void doCmdMem(char *params);
void doCmdNext(char *params);
void doCmdReadIO(char *params);
void doCmdReadMem(char *params);
void doCmdRegs(char *params);

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@ -1,6 +1,11 @@
#ifndef __DIS_DEFINES__
#define __DIS_DEFINES__
// The processor dependent config/status port
#define PDC_PORT PORTA
#define PDC_DDR DDRA
#define PDC_DIN PINA
unsigned int disassemble(unsigned int addr);
#endif

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@ -862,7 +862,13 @@ void disassem (unsigned int *ip) {
unsigned int disassemble(unsigned int addr) {
log0("%04X : ", addr);
disassem(&addr);
if (PDC_DIN & 0x80) {
log0("**NMI**");
} else if (PDC_DIN & 0x40) {
log0("**INT**");
} else {
disassem(&addr);
}
log0("\n");
return addr;
}

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@ -56,6 +56,9 @@ entity BusMonCore is
-- unused in pure bus monitor mode
Regs : in std_logic_vector(255 downto 0);
-- CPI Specific data
PdcData : in std_logic_vector(7 downto 0) := x"00";
-- CPU Memory Read/Write
-- unused in pure bus monitor mode
RdMemOut : out std_logic;
@ -182,15 +185,7 @@ begin
clk16M => clock_avr,
nrst => nrst_avr,
portain(0) => '0',
portain(1) => '0',
portain(2) => '0',
portain(3) => '0',
portain(4) => '0',
portain(5) => '0',
portain(6) => '0',
portain(7) => '0',
portain => PdcData,
portaout => open,
-- Command Port

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@ -117,6 +117,7 @@ entity T80 is
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
NMICycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic;
out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
@ -1170,6 +1171,7 @@ begin
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
NMICycle_n <= not NMICycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;

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@ -103,6 +103,7 @@ package T80_Pack is
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
NMICycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic;
REG : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A

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@ -72,8 +72,9 @@ entity T80a is
);
port(
-- Additions
TS : out std_logic_vector(2 downto 0);
Regs : out std_logic_vector(255 downto 0);
TS : out std_logic_vector(2 downto 0);
Regs : out std_logic_vector(255 downto 0);
PdcData : out std_logic_vector(7 downto 0);
-- Original Signals
RESET_n : in std_logic;
CLK_n : in std_logic;
@ -101,6 +102,7 @@ architecture rtl of T80a is
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal NMICycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
@ -175,6 +177,7 @@ begin
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
NMICycle_n => NMICycle_n,
REG => Regs(211 downto 0),
DIRSet => '0',
DIR => (others => '0')
@ -297,4 +300,7 @@ begin
end process;
TS <= TState;
PdcData <= (not NMICycle_n) & (not IntCycle_n) & "000000";
end;

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@ -121,6 +121,7 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
signal skipNextOpcode : std_logic;
signal Regs : std_logic_vector(255 downto 0);
signal PdcData : std_logic_vector(7 downto 0);
signal io_not_mem : std_logic;
signal io_rd : std_logic;
signal io_wr : std_logic;
@ -249,6 +250,7 @@ begin
tdin => tdin,
tcclk => tcclk,
Regs => Regs,
PdcData => PdcData,
RdMemOut => memory_rd,
WrMemOut => memory_wr,
RdIOOut => io_rd,
@ -270,6 +272,7 @@ begin
inst_t80: entity work.T80a port map (
TS => TState,
Regs => Regs,
PdcData => PdcData,
RESET_n => RESET_n_int,
CLK_n => cpu_clk,
CEN => cpu_clken,