6502: Make RES_n an input (it was bidirectional which is risky in some systems)

Change-Id: I91fbf429b5fb3ada181d73d7fd03ab36046657be

src/MOS6502CpuMon.vhd

@@ -44,7 +44,7 @@ entity MOS6502CpuMon is
         R_W_n           : out   std_logic;
         Data            : inout std_logic_vector(7 downto 0);
         SO_n            : in    std_logic;
-        Res_n           : inout std_logic;
+        Res_n           : in    std_logic;
         Rdy             : in    std_logic;
 
         -- External trigger inputs
@@ -95,9 +95,6 @@ architecture behavioral of MOS6502CpuMon is
     signal cpu_clk       : std_logic;
     signal busmon_clk    : std_logic;
 
-    signal Res_n_in      : std_logic;
-    signal Res_n_out     : std_logic;
-
 begin
 
     inst_dcm0 : entity work.DCM0
@@ -132,8 +129,7 @@ begin
         Din          => Din,
         Dout         => Dout,
         SO_n         => SO_n,
-        Res_n_in     => Res_n_in,
-        Res_n_out    => Res_n_out,
+        Res_n        => Res_n,
         Rdy          => Rdy_latched,
         trig         => trig,
         avr_RxD      => avr_RxD,
@@ -148,10 +144,6 @@ begin
         tcclk        => tcclk
     );
 
-    -- Tristate buffer driving reset back out
-    Res_n_in <= Res_n;
-    Res_n <= '0' when Res_n_out <= '0' else 'Z';
-
     sync_gen : process(cpu_clk)
     begin
         if rising_edge(cpu_clk) then

src/MOS6502CpuMonALS.vhd

@@ -52,7 +52,7 @@ entity MOS6502CpuMonALS is
         R_W_n            : out   std_logic_vector(1 downto 0);
         Data             : inout std_logic_vector(7 downto 0);
         SO_n             : in    std_logic;
-        Res_n            : inout std_logic;
+        Res_n            : in    std_logic;
         Rdy              : in    std_logic;
 
         -- 65C02 Signals

src/MOS6502CpuMonCore.vhd

@@ -45,8 +45,7 @@ entity MOS6502CpuMonCore is
         Din             : in    std_logic_vector(7 downto 0);
         Dout            : out   std_logic_vector(7 downto 0);
         SO_n            : in    std_logic;
-        Res_n_in        : in    std_logic;
-        Res_n_out       : out   std_logic;
+        Res_n           : in    std_logic;
         Rdy             : in    std_logic;
 
         -- External trigger inputs
@@ -86,6 +85,7 @@ architecture behavioral of MOS6502CpuMonCore is
     signal Wr_n_int      : std_logic;
     signal Sync_int      : std_logic;
     signal Addr_int      : std_logic_vector(23 downto 0);
+    signal Res_n_out     : std_logic;
 
     signal cpu_addr_us   : unsigned (15 downto 0);
     signal cpu_dout_us   : unsigned (7 downto 0);
@@ -134,7 +134,7 @@ begin
         WrIO_n       => '1',
         Sync         => Sync_int,
         Rdy          => open,
-        nRSTin       => Res_n_in,
+        nRSTin       => Res_n,
         nRSTout      => Res_n_out,
         CountCycle   => CountCycle,
         trig         => trig,
@@ -210,7 +210,7 @@ begin
             if reset_counter(reset_counter'high) = '0' then
                 reset_counter <= reset_counter + 1;
             end if;
-            cpu_reset_n <= Res_n_in and reset_counter(reset_counter'high);
+            cpu_reset_n <= Res_n and Res_n_out and reset_counter(reset_counter'high);
         end if;
     end process;
 

src/MOS6502CpuMonGODIL.vhd

@@ -43,7 +43,7 @@ entity MOS6502CpuMonGODIL is
         R_W_n            : out   std_logic;
         Data             : inout std_logic_vector(7 downto 0);
         SO_n             : in    std_logic;
-        Res_n            : inout std_logic;
+        Res_n            : in    std_logic;
         Rdy              : in    std_logic;
 
         -- External trigger inputs

src/MOS6502CpuMonLX9.vhd

@@ -43,7 +43,7 @@ entity MOS6502CpuMonLX9 is
         R_W_n            : out   std_logic;
         Data             : inout std_logic_vector(7 downto 0);
         SO_n             : in    std_logic;
-        Res_n            : inout std_logic;
+        Res_n            : in    std_logic;
         Rdy              : in    std_logic;
 
         -- External trigger inputs