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Z80: Fix timing of T80 IO cycles

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Change-Id: I769dcb01b95008b62455c86151252fdbd6d0aab5
This commit is contained in:
David Banks 2019-11-08 09:54:07 +00:00
parent 38c57c75a3
commit c8f997863e
1 changed files with 5 additions and 9 deletions
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14
src/T80/T80a.vhd
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@ -131,8 +131,8 @@ begin
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
WR_n_j <= WR_n_i; -- 0247a
RD_n_i <= not RD or (IORQ and IReq_Inhibit) or Req_Inhibit; -- DMB
WR_n_j <= WR_n_i or (IORQ and IReq_Inhibit); -- DMB
HALT_n <= HALT_n_int;
@ -212,7 +212,7 @@ begin
process (CLK_n) -- 0247a
begin
if CLK_n'event and CLK_n = '1' then
-- IReq_Inhibit <= not IORQ;
IReq_Inhibit <= (not IORQ) and IntCycle_n;
end if;
end process;
@ -229,7 +229,7 @@ begin
WR_n_i <= '1';
end if;
else
if TState = "001" and IORQ_n_i = '0' then
if TState = "001" then -- DMB
WR_n_i <= not Write;
elsif Tstate = "011" then
WR_n_i <= '1';
@ -295,11 +295,7 @@ begin
if TState = "001" and NoRead = '0' then
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
if IORQ = '0' then
RD <= not Write;
elsif IORQ_n_i = '0' then
RD <= not Write;
end if;
RD <= not Write; -- DMB
end if;
if TState = "011" then
RD <= '0';