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Fixed a problem with breakpoints running on one instruction on the Z80, version now 0.46

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Change-Id: I597087a8ed7d4da211c706e0c4972f5d037706ee
This commit is contained in:
David Banks
2015-06-29 17:16:23 +01:00
parent 8a2615d6b3
commit caec07483d
3 changed files with 19 additions and 13 deletions
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2
src/BusMonCore.vhd
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@@ -510,7 +510,7 @@ begin
if ((single = '0') or (cmd_edge2 = '0' and cmd_edge1 = '1' and cmd = "01000")) then
Rdy_int <= (not brkpt_active);
SS_Step <= '1';
SS_Step <= (not brkpt_active);
else
Rdy_int <= (not Sync);
end if;

10
src/Z80CpuMon.vhd
View File

@@ -226,10 +226,14 @@ begin
end if;
end if;
end process;
-- Make the monitoring decision in the middle of T2, but only if WAIT_n is '1'
Sync0 <= (WAIT_n_int and (not RD_n_int) and (not MREQ_n_int) and (not M1_n_int)) when TState = "010" else '0';
-- For instruction breakpoints, we make the monitoring decision as early as possibe
-- to allow time to stop the current instruction, which is possible because we don't
-- really care about the data (it's re-read from memory by the disassembler).
Sync0 <= not M1_n_int when TState = "001" else '0';
-- For reads/write breakpoints we make the monitoring decision in the middle of T2
-- but only if WAIT_n is '1' so we catch the right data.
Read_n0 <= not (WAIT_n_int and (not RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
Write_n0 <= not (WAIT_n_int and (not WR_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';