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Updated XDM2Kx8 to a more portable implementation

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Change-Id: I37cbe56b7b0113e24855eb1c0fcf7bbe006eefd3
This commit is contained in:
David Banks 2015-11-28 11:19:27 +00:00
parent d70c378245
commit cc6c062b4b
1 changed files with 37 additions and 66 deletions
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103
src/AVR8/Memory/XDM2Kx8.vhd
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@ -1,66 +1,37 @@
--************************************************************************************************
-- 2Kx8(16 KB) DM RAM for AVR Core(Xilinx)
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Jack Gassett for use with Papilio
-- Modified 30.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XDM2Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(CDATAMEMSIZE downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end XDM2Kx8;
architecture RTL of XDM2Kx8 is
signal RAMBlDOut : std_logic_vector(dout'range);
signal WEB : std_logic;
signal cp2n : std_logic;
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB <= '1' when we='1' else '0';
RAM_Byte:component RAMB16_S9 port map(
DO => RAMBlDOut(7 downto 0),
ADDR => address(10 downto 0),
DI => din(7 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB
);
-- Output data mux
dout <= RAMBlDOut;
end RTL;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
entity XDM2Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(CDATAMEMSIZE downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end XDM2Kx8;
architecture RTL of XDM2Kx8 is
type ram_type is array (2**(CDATAMEMSIZE+1)-1 downto 0) of std_logic_vector (7 downto 0);
signal RAM : ram_type;
begin
process (cp2)
begin
if rising_edge(cp2) then
if ce = '1' then
if (we = '1') then
RAM(conv_integer(address)) <= din;
end if;
dout <= RAM(conv_integer(address));
end if;
end if;
end process;
end RTL;