diff --git a/src/Z80CpuMon10CL006Kakigate.vhd b/src/Z80CpuMon10CL006Kakigate.vhd new file mode 100644 index 0000000..00c73fa --- /dev/null +++ b/src/Z80CpuMon10CL006Kakigate.vhd @@ -0,0 +1,208 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 2026 David Banks +-- +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / +-- \ \ \/ +-- \ \ +-- / / Filename : Z80CpuMon10CL006Kakigate.vhd +-- /___/ /\ Timestamp : 03/02/2026 +-- \ \ / \ +-- \___\/\___\ +-- +--Design Name: Z80CpuMon10CL006Kakigate +--Device: 10CL006Kakigate8 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity Z80CpuMon10CL006Kakigate is + generic ( + num_comparators : integer := 8; -- default value for lx9core board + avr_prog_mem_size : integer := 1024 * 9 -- default value for lx9core board + ); + port ( + clock : in std_logic; + + -- Z80 Signals + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + Addr : out std_logic_vector(15 downto 0); + Data : inout std_logic_vector(7 downto 0); + + -- Level Shifers Controls + OEC_n : out std_logic; + OEA1_n : out std_logic; + OEA2_n : out std_logic; + OED_n : out std_logic; + DIRD : out std_logic; + + -- External trigger inputs + trig : in std_logic_vector(1 downto 0); + + -- ID/mode inputs + mode : in std_logic; + id : in std_logic_vector(3 downto 0); + + -- Power monitoring + monitor_uv_n : in std_logic; + monitor_ov_n : in std_logic; + + -- Serial Console + avr_RxD : in std_logic; + avr_TxD : out std_logic; + + -- Switches + sw : in std_logic_vector(4 downto 2); + + -- LEDs + led : out std_logic_vector(4 downto 1) + ); +end Z80CpuMon10CL006Kakigate; + +architecture behavioral of Z80CpuMon10CL006Kakigate is + + signal MREQ_n_int : std_logic; + signal IORQ_n_int : std_logic; + signal M1_n_int : std_logic; + signal RD_n_int : std_logic; + signal WR_n_int : std_logic; + signal RFSH_n_int : std_logic; + signal HALT_n_int : std_logic; + signal BUSAK_n_int : std_logic; + signal tristate_n : std_logic; + signal tristate_ad_n: std_logic; + + signal sw_reset_cpu : std_logic; + signal sw_reset_avr : std_logic; + signal led_bkpt : std_logic; + signal led_trig0 : std_logic; + signal led_trig1 : std_logic; + + -- 50MHz clock, toggle every 25,000,000 = + signal blinky_count : unsigned(24 downto 0) := (others => '0'); + signal led_blinky : std_logic := '0'; + +begin + + -- Switches are active low + sw_reset_cpu <= not sw(2); + sw_reset_avr <= not sw(3); + + -- LEDs are active low + led(1) <= not led_bkpt; + led(2) <= (not led_trig0) and monitor_ov_n; + led(3) <= (not led_trig1) and monitor_uv_n; + led(4) <= led_blinky and sw(2) and sw(3); + + -- 1Hz Blinky LED + process(clock) + begin + if rising_edge(clock) then + if blinky_count = to_unsigned(24999999, blinky_count'length) then + blinky_count <= (others => '0'); + led_blinky <= not led_blinky; + else + blinky_count <= blinky_count + 1; + end if; + end if; + end process; + + wrapper : entity work.Z80CpuMon + generic map ( + ClkMult => 12, + ClkDiv => 25, + ClkPer => 20.000, + num_comparators => num_comparators, + avr_prog_mem_size => avr_prog_mem_size + ) + port map ( + clock => clock, + + -- Z80 Signals + RESET_n => RESET_n, + CLK_n => CLK_n, + WAIT_n => WAIT_n, + INT_n => INT_n, + NMI_n => NMI_n, + BUSRQ_n => BUSRQ_n, + M1_n => M1_n_int, + MREQ_n => MREQ_n_int, + IORQ_n => IORQ_n_int, + RD_n => RD_n_int, + WR_n => WR_n_int, + RFSH_n => RFSH_n_int, + HALT_n => HALT_n_int, + BUSAK_n => BUSAK_n_int, + Addr => Addr, + Data => Data, + + -- Buffer Control Signals + DIRD => DIRD, + tristate_n => tristate_n, + tristate_ad_n => tristate_ad_n, + + -- Mode jumper, tie low to generate NOPs when paused + mode => mode, + + -- External trigger inputs + trig => trig, + + -- Serial Console + avr_RxD => avr_RxD, + avr_TxD => avr_TxD, + + -- Switches + sw_reset_cpu => sw_reset_cpu, + sw_reset_avr => sw_reset_avr, + + -- LEDs + led_bkpt => led_bkpt, + led_trig0 => led_trig0, + led_trig1 => led_trig1, + + -- OHO_DY1 connected to test connector + tmosi => open, + tdin => open, + tcclk => open, + + -- Debugging signals + test1 => open, + test2 => open, + test3 => open, + test4 => open + ); + + -- Z80 Outputs + MREQ_n <= MREQ_n_int; + IORQ_n <= IORQ_n_int; + M1_n <= M1_n_int; + RD_n <= RD_n_int; + WR_n <= WR_n_int; + RFSH_n <= RFSH_n_int; + HALT_n <= HALT_n_int; + BUSAK_n <= BUSAK_n_int; + + -- Level Shifter Controls + OEC_n <= not tristate_n; + OEA1_n <= not tristate_ad_n; + OEA2_n <= not tristate_ad_n; + OED_n <= not tristate_ad_n; + +end behavioral; diff --git a/target/10CL006Kakigate/Makefile b/target/10CL006Kakigate/Makefile new file mode 100644 index 0000000..8e5b22a --- /dev/null +++ b/target/10CL006Kakigate/Makefile @@ -0,0 +1 @@ +include ../common/Makefile_subdirs.inc diff --git a/target/10CL006Kakigate/icez80/Makefile b/target/10CL006Kakigate/icez80/Makefile new file mode 100644 index 0000000..6c9b039 --- /dev/null +++ b/target/10CL006Kakigate/icez80/Makefile @@ -0,0 +1,22 @@ +# The root directory of the project +ROOT = ../../.. + +# The common directory for makefile includes, etc. +COMMON = ../../common + +# The target bitstream file to be generated including the monitor program +TARGET = icez80 + +# Frequuency that the AVR runs at +F_CPU = 24000000 + +# Default Baud Rate of serial interface +# Note: F_CPU / 16 / BAUD need to be close to an integer +BAUD = 115200 + +# Size of the XPM Memory in words +XPM_SIZE = 9216 + +# Common include files +include $(COMMON)/Makefile_$(TARGET).inc +include $(COMMON)/Makefile_Altera.inc diff --git a/target/10CL006Kakigate/icez80/icez80.qpf b/target/10CL006Kakigate/icez80/icez80.qpf new file mode 100644 index 0000000..da6e717 --- /dev/null +++ b/target/10CL006Kakigate/icez80/icez80.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition +# Date created = 14:44:08 November 25, 2025 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "20.1" +DATE = "14:44:08 November 25, 2025" + +# Revisions + +PROJECT_REVISION = "icez80" diff --git a/target/10CL006Kakigate/icez80/icez80.qsf b/target/10CL006Kakigate/icez80/icez80.qsf new file mode 100644 index 0000000..f684cf2 --- /dev/null +++ b/target/10CL006Kakigate/icez80/icez80.qsf @@ -0,0 +1,241 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition +# Date created = 14:44:09 November 25, 2025 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Z80CpuMonCycloneIV_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone 10 LP" +set_global_assignment -name DEVICE 10CL006YE144C8G +set_global_assignment -name TOP_LEVEL_ENTITY Z80CpuMon10CL006Kakigate +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:44:09 NOVEMBER 25, 2025" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" + +set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/avr_adr_pack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/AVRuCPackage.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/spi_mod_comp_pack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/std_library.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/SynthCtrlPack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/alu_avr.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/AVR_Core_CompPack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/avr_core.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/bit_processor.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/io_adr_dec.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/io_reg_file.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/pm_fetch_dec.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/reg_file.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGProgrammerPack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGTAPCtrlSMPack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/ArbiterAndMux.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/MemAccessCompPack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/MemRdMux.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/RAMAdrDcd.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Memory/XDM_Generic.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Memory/XPM_Altera.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/portx.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/SynchronizerCompPack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/SynchronizerDFF.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/SynchronizerLatch.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/Timer_Counter.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/uart.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/resync/rsnc_bit.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/resync/rsnc_comp_pack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/spi_mod/spi_mod.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/spi_mod/spi_slv_sel.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/AVR8.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/AVR_uC_CompPack.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/external_mux.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/ExtIRQ_Controller.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/RAMDataReg.vhd +set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/ResetGenerator.vhd +set_global_assignment -name VHDL_FILE ../../../src/BusMonCore.vhd +set_global_assignment -name VHDL_FILE ../../../src/altera/DCM0.vhd +set_global_assignment -name VHDL_FILE ../../../src/altera/WatchEvents_CycloneIV.vhd +set_global_assignment -name VHDL_FILE ../../../src/oho_dy1/Oho_Dy1.vhd +set_global_assignment -name VHDL_FILE ../../../src/oho_dy1/OhoPack.vhd +set_global_assignment -name VHDL_FILE ../../../src/T80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE ../../../src/T80/T80a.vhd +set_global_assignment -name VHDL_FILE ../../../src/T80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE ../../../src/T80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE ../../../src/T80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE ../../../src/T80/T80.vhd +set_global_assignment -name VHDL_FILE ../../../src/Z80CpuMon10CL006Kakigate.vhd +set_global_assignment -name VHDL_FILE ../../../src/Z80CpuMon.vhd +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" + +# Allow reserved pin 101 (Altera_nCEO) to be used as a normal IO (for LED1) +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# On-board peripherals +set_location_assignment PIN_91 -to clock +set_location_assignment PIN_11 -to avr_TxD +set_location_assignment PIN_10 -to avr_RxD +set_location_assignment PIN_89 -to sw[2] +set_location_assignment PIN_90 -to sw[3] +set_location_assignment PIN_88 -to sw[4] +set_location_assignment PIN_101 -to led[1] +set_location_assignment PIN_100 -to led[2] +set_location_assignment PIN_99 -to led[3] +set_location_assignment PIN_98 -to led[4] + +# DIP Pins 1..20 +set_location_assignment PIN_28 -to Addr[11] +set_location_assignment PIN_32 -to Addr[12] +set_location_assignment PIN_34 -to Addr[13] +set_location_assignment PIN_39 -to Addr[14] +set_location_assignment PIN_43 -to Addr[15] +set_location_assignment PIN_22 -to CLK_n +set_location_assignment PIN_51 -to Data[4] +set_location_assignment PIN_52 -to Data[3] +set_location_assignment PIN_53 -to Data[5] +set_location_assignment PIN_54 -to Data[6] +set_location_assignment PIN_55 -to Data[2] +set_location_assignment PIN_58 -to Data[7] +set_location_assignment PIN_59 -to Data[0] +set_location_assignment PIN_60 -to Data[1] +set_location_assignment PIN_103 -to INT_n +set_location_assignment PIN_112 -to NMI_n +set_location_assignment PIN_121 -to HALT_n +set_location_assignment PIN_76 -to MREQ_n +set_location_assignment PIN_77 -to IORQ_n + +# DIP Pins 40..21 +set_location_assignment PIN_7 -to Addr[10] +set_location_assignment PIN_1 -to Addr[9] +set_location_assignment PIN_143 -to Addr[8] +set_location_assignment PIN_141 -to Addr[7] +set_location_assignment PIN_142 -to Addr[6] +set_location_assignment PIN_137 -to Addr[5] +set_location_assignment PIN_31 -to Addr[4] +set_location_assignment PIN_33 -to Addr[3] +set_location_assignment PIN_38 -to Addr[2] +set_location_assignment PIN_144 -to Addr[1] +set_location_assignment PIN_2 -to Addr[0] +set_location_assignment PIN_125 -to RFSH_n +set_location_assignment PIN_120 -to M1_n +set_location_assignment PIN_25 -to RESET_n +set_location_assignment PIN_106 -to BUSRQ_n +set_location_assignment PIN_105 -to WAIT_n +set_location_assignment PIN_115 -to BUSAK_n +set_location_assignment PIN_74 -to WR_n +set_location_assignment PIN_75 -to RD_n + +# Level shifter controls mapped to spare pins on Connectors A and B +set_location_assignment PIN_42 -to OEA1_n +set_location_assignment PIN_3 -to OEA2_n +set_location_assignment PIN_66 -to OED_n +set_location_assignment PIN_65 -to DIRD +set_location_assignment PIN_80 -to OEC_n + +# Misc +set_location_assignment PIN_23 -to trig[1] +set_location_assignment PIN_24 -to trig[0] +set_location_assignment PIN_124 -to id[3] +set_location_assignment PIN_127 -to id[2] +set_location_assignment PIN_126 -to id[1] +set_location_assignment PIN_129 -to id[0] +set_location_assignment PIN_84 -to mode +set_location_assignment PIN_86 -to monitor_ov_n +set_location_assignment PIN_87 -to monitor_uv_n + +# Output drive strengths +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to M1_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to MREQ_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IORQ_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to RD_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to WR_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to RFSH_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to HALT_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to BUSAK_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to OEC_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to OEA1_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to OEA2_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to OED_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DIRD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to avr_TxD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[7] diff --git a/target/10CL006Kakigate/icez80/icez80.sdc b/target/10CL006Kakigate/icez80/icez80.sdc new file mode 100644 index 0000000..96086ad --- /dev/null +++ b/target/10CL006Kakigate/icez80/icez80.sdc @@ -0,0 +1,38 @@ +#************************************************************** +# Create Clock +#************************************************************** + +# External 50MHz clock input from on-board crystal +create_clock -period "50 MHz" -name clock_50 [get_ports clock] + +# Z80 CLK_n clock input +create_clock -period "16 MHz" -name clock_clk [get_ports CLK_n] + +# Trig(0) clock input +create_clock -period "16 MHz" -name clock_trig0 [get_ports TRIG[0]] + +#************************************************************** +# Create Generated Clock +#************************************************************** + +# Doing this manually above so we can name the clock +# derive_pll_clocks + +#create_generated_clock -source {wrapper|inst_dcm0|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 25 -multiply_by 12 -duty_cycle 50.00 -name clock_avr {wrapper|inst_dcm0|altpll_component|auto_generated|pll1|clk[0]} + +create_generated_clock -source [get_ports clock] -divide_by 25 -multiply_by 12 -duty_cycle 50.00 -name clock_avr {wrapper|inst_dcm0|altpll_component|auto_generated|pll1|clk[0]} + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** +derive_clock_uncertainty + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group {clock_avr} -group {clock_clk} +set_clock_groups -asynchronous -group {clock_clk} -group {clock_avr} + +set_clock_groups -asynchronous -group {clock_avr} -group {clock_trig0} +set_clock_groups -asynchronous -group {clock_trig0} -group {clock_avr}