diff --git a/src/MC6809CpuMonLX9.vhd b/src/MC6809CpuMonLX9.vhd
index ee3d0be..7f03f27 100644
--- a/src/MC6809CpuMonLX9.vhd
+++ b/src/MC6809CpuMonLX9.vhd
@@ -26,7 +26,7 @@ entity MC6809CpuMonLX9 is
        avr_prog_mem_size : integer := 1024 * 9  -- default value correct for LX9
        );
     port (
-        clock49         : in    std_logic;
+        clock           : in    std_logic;
 
         -- A locally generated test clock
         -- 1.8457 MHz in E     Mode (6809E) so it can drive E     (PIN34)
@@ -132,7 +132,7 @@ begin
       port map (
 
         -- Fast clock
-        clock           => clock49,
+        clock           => clock,
 
         -- Quadrature clocks
         E               => E,
diff --git a/src/Z80CpuMon.vhd b/src/Z80CpuMon.vhd
index c1bf49d..dedffc0 100644
--- a/src/Z80CpuMon.vhd
+++ b/src/Z80CpuMon.vhd
@@ -29,7 +29,7 @@ entity Z80CpuMon is
        avr_prog_mem_size : integer
        );
     port (
-        clock49         : in    std_logic;
+        clock           : in    std_logic;
 
         -- Z80 Signals
         RESET_n         : in    std_logic;
@@ -204,7 +204,7 @@ begin
         ClkPer       => ClkPer
       )
       port map(
-        CLKIN_IN     => clock49,
+        CLKIN_IN     => clock,
         CLKFX_OUT    => clock_avr
       );
 
@@ -435,9 +435,9 @@ begin
 --
 -- If the problem recurs, we should switch to something like:
 --
---    addr_delay : process(clock49)
+--    addr_delay : process(clock)
 --    begin
---        if rising_edge(clock49) then
+--        if rising_edge(clock) then
 --            Addr2 <= Addr1;
 --            Addr <= Addr2;
 --        end if;
diff --git a/src/Z80CpuMonALS.vhd b/src/Z80CpuMonALS.vhd
index 777f0eb..3355461 100644
--- a/src/Z80CpuMonALS.vhd
+++ b/src/Z80CpuMonALS.vhd
@@ -133,7 +133,7 @@ begin
             avr_prog_mem_size => avr_prog_mem_size
             )
         port map (
-            clock49           => clock,
+            clock             => clock,
 
             -- Z80 Signals
             RESET_n           => RESET_n,
diff --git a/src/Z80CpuMonGODIL.vhd b/src/Z80CpuMonGODIL.vhd
index 33256c9..7941e20 100644
--- a/src/Z80CpuMonGODIL.vhd
+++ b/src/Z80CpuMonGODIL.vhd
@@ -118,7 +118,7 @@ begin
             avr_prog_mem_size => avr_prog_mem_size
             )
         port map(
-            clock49         =>  clock49,
+            clock           =>  clock49,
 
             -- Z80 Signals
             RESET_n         =>  RESET_n,
diff --git a/src/Z80CpuMonLX9.vhd b/src/Z80CpuMonLX9.vhd
index fd67b6f..19a408d 100644
--- a/src/Z80CpuMonLX9.vhd
+++ b/src/Z80CpuMonLX9.vhd
@@ -26,7 +26,7 @@ entity Z80CpuMonLX9 is
         avr_prog_mem_size : integer := 1024 * 16 -- default value correct for LX9
         );
     port (
-        clock49         : in    std_logic;
+        clock           : in    std_logic;
 
         -- Z80 Signals
         RESET_n         : in    std_logic;
@@ -119,7 +119,7 @@ begin
             avr_prog_mem_size => avr_prog_mem_size
             )
         port map(
-            clock49         =>  clock49,
+            clock           =>  clock,
 
             -- Z80 Signals
             RESET_n         =>  RESET_n,
diff --git a/target/lx9_jason/ice6809/board.ucf b/target/lx9_jason/ice6809/board.ucf
index 0fc97a8..72e520b 100644
--- a/target/lx9_jason/ice6809/board.ucf
+++ b/target/lx9_jason/ice6809/board.ucf
@@ -4,7 +4,7 @@ NET "E" CLOCK_DEDICATED_ROUTE = FALSE;
 # This is only needed because of the the clock_test output
 PIN "inst_dcm1/CLKFX_BUFG_INST.O" CLOCK_DEDICATED_ROUTE = FALSE;
 
-NET "clock49"  LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
+NET "clock"      LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
 #NET "VSS"       LOC="P94"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
 NET "NMI_n"      LOC="P95"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
@@ -76,7 +76,7 @@ NET "test2"    LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; #
 #NET "test4"   LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led5
 #NET "test5"   LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led7
 
-# A clock generated from the 50.000MHz clock 
+# A clock generated from the 50.000MHz clock
 NET "clock_test" LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
 
 # A jumper to enable 6809E mode
diff --git a/target/lx9_jason/icez80/board.ucf b/target/lx9_jason/icez80/board.ucf
index 513d7f9..7d0a1e1 100644
--- a/target/lx9_jason/icez80/board.ucf
+++ b/target/lx9_jason/icez80/board.ucf
@@ -4,7 +4,7 @@ TIMESPEC TS_clk_period_clk_n = PERIOD "clk_period_grp_clk_n" 250ns LOW;
 
 NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
 
-NET "clock49"  LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
+NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
 NET "Addr<11>" LOC="P94"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
 NET "Addr<12>" LOC="P95"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
diff --git a/target/lx9_jason_flipped/ice6809/board.ucf b/target/lx9_jason_flipped/ice6809/board.ucf
index 5895b28..297e233 100644
--- a/target/lx9_jason_flipped/ice6809/board.ucf
+++ b/target/lx9_jason_flipped/ice6809/board.ucf
@@ -4,7 +4,7 @@ NET "E" CLOCK_DEDICATED_ROUTE = FALSE;
 # This is only needed because of the the clock_test output
 PIN "inst_dcm1/CLKFX_BUFG_INST.O" CLOCK_DEDICATED_ROUTE = FALSE;
 
-NET "clock49"  LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
+NET "clock"      LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
 #NET "VSS"       LOC="P16"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
 NET "NMI_n"      LOC="P15"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
@@ -76,7 +76,7 @@ NET "test2"    LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; #
 #NET "test4"   LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led5
 #NET "test5"   LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # led7
 
-# A clock generated from the 50.000MHz clock 
+# A clock generated from the 50.000MHz clock
 NET "clock_test" LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
 
 # A jumper to enable 6809E mode
diff --git a/target/lx9_jason_flipped/icez80/board.ucf b/target/lx9_jason_flipped/icez80/board.ucf
index 6b0ea25..796c663 100644
--- a/target/lx9_jason_flipped/icez80/board.ucf
+++ b/target/lx9_jason_flipped/icez80/board.ucf
@@ -4,7 +4,7 @@ TIMESPEC TS_clk_period_clk_n = PERIOD "clk_period_grp_clk_n" 250ns LOW;
 
 NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
 
-NET "clock49"  LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
+NET "clock"    LOC="P50"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns        ; # 50.00 MHz Oscillator
 
 NET "Addr<11>" LOC="P16"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
 NET "Addr<12>" LOC="P15"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2