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Z80: push tristating up to Z80CpuMon

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Change-Id: I6fd3e0a170f908d47a7cf0a7f82ab4f74ed980d9
This commit is contained in:
David Banks 2019-11-01 18:31:31 +00:00
parent 71cb5ff561
commit d23ebe6913
2 changed files with 48 additions and 19 deletions
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22
src/T80/T80a.vhd
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@ -135,12 +135,22 @@ begin
WR_n_j <= WR_n_i; -- 0247a WR_n_j <= WR_n_i; -- 0247a
HALT_n <= HALT_n_int; HALT_n <= HALT_n_int;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i or IReq_Inhibit when BUSAK_n_i = '1' else 'Z'; -- 0247a --Remove tristate as in ICE-Z80 this is implmeneted in Z80CpuMon
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z'; --MREQ_n <= MREQ_n_i; when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_j when BUSAK_n_i = '1' else 'Z'; -- 0247a --IORQ_n <= IORQ_n_i or IReq_Inhibit when BUSAK_n_i = '1' else 'Z'; -- 0247a
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z'; --RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z'); --WR_n <= WR_n_j when BUSAK_n_i = '1' else 'Z'; -- 0247a
--RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
--A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
MREQ_n <= MREQ_n_i;
IORQ_n <= IORQ_n_i or IReq_Inhibit; -- 0247a
RD_n <= RD_n_i;
WR_n <= WR_n_j; -- 0247a
RFSH_n <= RFSH_n_i;
A <= A_i;
Dout <= DO; Dout <= DO;
Den <= Write and BUSAK_n_i; Den <= Write and BUSAK_n_i;

45
src/Z80CpuMon.vhd
View File

@ -110,6 +110,7 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
signal RFSH_n_int : std_logic; signal RFSH_n_int : std_logic;
signal M1_n_int : std_logic; signal M1_n_int : std_logic;
signal BUSAK_n_int : std_logic; signal BUSAK_n_int : std_logic;
signal BUSAK_n_comb : std_logic;
signal WAIT_n_latched : std_logic; signal WAIT_n_latched : std_logic;
signal TState : std_logic_vector(2 downto 0); signal TState : std_logic_vector(2 downto 0);
signal TState1 : std_logic_vector(2 downto 0); signal TState1 : std_logic_vector(2 downto 0);
@ -416,19 +417,35 @@ begin
-- TODO: Also need to take account of BUSRQ_n/BUSAK_n -- TODO: Also need to take account of BUSRQ_n/BUSAK_n
MREQ_n <= MREQ_n_int when state = idle else mon_mreq_n and mon_xx_n; MREQ_n <= 'Z' when BUSAK_n_comb = '0' else
IORQ_n <= IORQ_n_int when state = idle else mon_iorq_n; MREQ_n_int when state = idle else
RFSH_n <= RFSH_n_int when state = idle else mon_rfsh_n; mon_mreq_n and mon_xx_n;
WR_n <= WR_n_int when state = idle else mon_wr_n;
RD_n <= RD_n_int when state = idle else mon_rd_n and mon_xx_n;
M1_n <= M1_n_int when state = idle else mon_m1_n;
BUSAK_n <= BUSAK_n_int when state = idle else mon_busak_n;
Addr <= x"0000" when state = nop_t1 or state = nop_t2 else IORQ_n <= 'Z' when BUSAK_n_comb = '0' else
rfsh_addr when state = nop_t3 or state = nop_t4 else IORQ_n_int when state = idle else
memory_addr when state /= idle else mon_iorq_n;
WR_n <= 'Z' when BUSAK_n_comb = '0' else
WR_n_int when state = idle else
mon_wr_n;
RD_n <= 'Z' when BUSAK_n_comb = '0' else
RD_n_int when state = idle else
mon_rd_n and mon_xx_n;
RFSH_n <= RFSH_n_int when state = idle else mon_rfsh_n;
M1_n <= M1_n_int when state = idle else mon_m1_n;
Addr <= (others => 'Z') when BUSAK_n_comb = '0' else
x"0000" when state = nop_t1 or state = nop_t2 else
rfsh_addr when state = nop_t3 or state = nop_t4 else
memory_addr when state /= idle else
Addr_int; Addr_int;
BUSAK_n_comb <= BUSAK_n_int when state = idle else mon_busak_n;
BUSAK_n <= BUSAK_n_comb;
-- The Acorn Z80 Second Processor needs ~10ns of address hold time following M1 -- The Acorn Z80 Second Processor needs ~10ns of address hold time following M1
-- and MREQ being released at the start of T3. Otherwise, the ROM switching -- and MREQ being released at the start of T3. Otherwise, the ROM switching
-- during NMI doesn't work reliably due to glitches. See: -- during NMI doesn't work reliably due to glitches. See:
@ -448,11 +465,13 @@ begin
-- end if; -- end if;
-- end process; -- end process;
Data <= memory_dout when state = wr_wa or state = wr_t2 or state = wr_t3 else Data <= (others => 'Z') when BUSAK_n_comb = '0' else
Dout when state = idle and Den = '1' else memory_dout when state = wr_wa or state = wr_t2 or state = wr_t3 else
Dout when state = idle and Den = '1' else
(others => 'Z'); (others => 'Z');
DOE_n <= '0' when state = wr_wa or state = wr_t2 or state = wr_t3 else DOE_n <= '1' when BUSAK_n_comb = '0' else
'0' when state = wr_wa or state = wr_t2 or state = wr_t3 else
'0' when state = idle and Den = '1' else '0' when state = idle and Den = '1' else
'1'; '1';