Changed to 18K ROM/2K RAM, version now 0.60, bitfiles published for all three designs

Change-Id: I2dd2b203e68d3ddde7d8bbb9052d4d46b802fbbb

AtomCpuMon.xise

@@ -162,18 +162,10 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
-    <file xil_pn:name="src/AVR8/Memory/XDM4Kx8.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
-    </file>
     <file xil_pn:name="src/AVR8/Memory/XMemCompPack.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
     </file>
-    <file xil_pn:name="src/AVR8/Memory/XPM8Kx16.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
-    </file>
     <file xil_pn:name="src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
@@ -261,6 +253,14 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
     </file>
+    <file xil_pn:name="src/AVR8/Memory/XDM2Kx8.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
+    </file>
+    <file xil_pn:name="src/AVR8/Memory/XPM9Kx16.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="121"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+    </file>
     <file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>

MC6809ECpuMon.xise

@@ -150,14 +150,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
     </file>
-    <file xil_pn:name="src/AVR8/Memory/XDM4Kx8.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
-    </file>
-    <file xil_pn:name="src/AVR8/Memory/XPM8Kx16.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
-    </file>
     <file xil_pn:name="src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
@@ -237,6 +229,14 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
     </file>
+    <file xil_pn:name="src/AVR8/Memory/XDM2Kx8.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
+    </file>
+    <file xil_pn:name="src/AVR8/Memory/XPM9Kx16.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+    </file>
     <file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>

Z80CpuMon.xise

@@ -182,14 +182,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
     </file>
-    <file xil_pn:name="src/AVR8/Memory/XDM4Kx8.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
-    </file>
-    <file xil_pn:name="src/AVR8/Memory/XPM8Kx16.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
-    </file>
     <file xil_pn:name="src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
@@ -265,6 +257,14 @@
     <file xil_pn:name="src/Z80CpuMon.bmm" xil_pn:type="FILE_BMM">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="src/AVR8/Memory/XDM2Kx8.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
+    </file>
+    <file xil_pn:name="src/AVR8/Memory/XPM9Kx16.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+    </file>
     <file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>

firmware/AtomBusMon.c

@@ -10,7 +10,7 @@
  * VERSION and NAME are used in the start-up message
  ********************************************************/
 
-#define VERSION "0.53"
+#define VERSION "0.60"
 
 #if (CPU == Z80)
   #define NAME "ICE-T80"
@@ -28,11 +28,9 @@
 
 #ifdef CPUEMBEDDED
   #if (CPU == Z80)
-    #define NUM_CMDS 28
+    #define NUM_CMDS 29
-  #elif (CPU == 6502)
-    #define NUM_CMDS 22
   #else
-    #define NUM_CMDS 21
+    #define NUM_CMDS 22
   #endif
 #else
   #define NUM_CMDS 14
@@ -58,9 +56,7 @@ char *cmdStrings[NUM_CMDS] = {
   "rdi",
   "wri",
 #endif
-#if (CPU == 6502)
   "test",
-#endif
 #endif
   "reset",
   "step",
@@ -99,9 +95,7 @@ void (*cmdFuncs[NUM_CMDS])(char *params) = {
   doCmdReadIO,
   doCmdWriteIO,
 #endif
-#if (CPU == 6502)
   doCmdTest,
-#endif
 #endif
   doCmdReset,
   doCmdStep,
@@ -370,7 +364,7 @@ int             triggers[MAXBKPTS];
 
 #define NUM_TRIGGERS 16
 
-char *triggerStrings[NUM_TRIGGERS] = {
+char * triggerStrings[NUM_TRIGGERS] = {
   "Never",
   "~T0 and ~T1",
   "T0 and ~T1",
@@ -831,7 +825,6 @@ void genericBreakpoint(char *params, unsigned int mode) {
  ********************************************************/
 
 #ifdef CPUEMBEDDED
-#if (CPU == 6502)
 char *testNames[6] = {
   "Fixed",
   "Checkerboard",
@@ -904,7 +897,6 @@ void test(unsigned int start, unsigned int end, int data) {
     log0(": passed\n");
   }
 }
-#endif
 #endif // CPUEMBEDDED
 
 /*******************************************
@@ -946,11 +938,23 @@ void doCmdStep(char *params) {
 
 void doCmdReset(char *params) {
   log0("Resetting CPU\n");
+#if (CPU == 6502)
+  // For the 6502 cores, to get the single stepping to stop correctly
+  // on the first instruction after reset, it helps to assert reset twice.
+  // I haven't looked into why this is, as it doesn't seem very important.
+  // It's mostly cosmetic, but nice on the Atom to consisently show FF3F.
+  int i;
+  for (i = 0; i < 2; i++) { 
+#endif
    hwCmd(CMD_RESET, 1);
    Delay_us(50);
    hwCmd(CMD_STEP, 0);
    Delay_us(50);
    hwCmd(CMD_RESET, 0);
+   Delay_us(50);
+#if (CPU == 6502)
+  }
+#endif
   logAddr();
 }
 
@@ -1031,8 +1035,6 @@ void doCmdWriteIO(char *params) {
 
 #endif
 
-#if (CPU == 6502)
-
 void doCmdTest(char *params) {
   unsigned int start;
   unsigned int end;
@@ -1051,8 +1053,6 @@ void doCmdTest(char *params) {
   }
 }
 
-#endif
-
 #endif // CPUEMBEDDED
 
 void doCmdTrace(char *params) {

firmware/dis6502.c

@@ -1,3 +1,4 @@
+#include <avr/pgmspace.h>
 #include "AtomBusMon.h"
 
 enum
@@ -76,77 +77,77 @@ enum
     I_XXX
   };
 
-char *opStrings[67] = {
+static const char opString[] PROGMEM = "\
-    "ADC",
+ADC\
-    "AND",
+AND\
-    "ASL",
+ASL\
-    "BCC",
+BCC\
-    "BCS",
+BCS\
-    "BEQ",
+BEQ\
-    "BIT",
+BIT\
-    "BMI",
+BMI\
-    "BNE",
+BNE\
-    "BPL",
+BPL\
-    "BRA",
+BRA\
-    "BRK",
+BRK\
-    "BVC",
+BVC\
-    "BVS",
+BVS\
-    "CLC",
+CLC\
-    "CLD",
+CLD\
-    "CLI",
+CLI\
-    "CLV",
+CLV\
-    "CMP",
+CMP\
-    "CPX",
+CPX\
-    "CPY",
+CPY\
-    "DEC",
+DEC\
-    "DEX",
+DEX\
-    "DEY",
+DEY\
-    "EOR",
+EOR\
-    "INC",
+INC\
-    "INX",
+INX\
-    "INY",
+INY\
-    "JMP",
+JMP\
-    "JSR",
+JSR\
-    "LDA",
+LDA\
-    "LDX",
+LDX\
-    "LDY",
+LDY\
-    "LSR",
+LSR\
-    "NOP",
+NOP\
-    "ORA",
+ORA\
-    "PHA",
+PHA\
-    "PHP",
+PHP\
-    "PHX",
+PHX\
-    "PHY",
+PHY\
-    "PLA",
+PLA\
-    "PLP",
+PLP\
-    "PLX",
+PLX\
-    "PLY",
+PLY\
-    "ROL",
+ROL\
-    "ROR",
+ROR\
-    "RTI",
+RTI\
-    "RTS",
+RTS\
-    "SBC",
+SBC\
-    "SEC",
+SEC\
-    "SED",
+SED\
-    "SEI",
+SEI\
-    "STA",
+STA\
-    "STP",
+STP\
-    "STX",
+STX\
-    "STY",
+STY\
-    "STZ",
+STZ\
-    "TAX",
+TAX\
-    "TAY",
+TAY\
-    "TRB",
+TRB\
-    "TSB",
+TSB\
-    "TSX",
+TSX\
-    "TXA",
+TXA\
-    "TXS",
+TXS\
-    "TYA",
+TYA\
-    "WAI",
+WAI\
-    "---"
+---\
-};
+";
 
-unsigned char dopname[256] =
+static const unsigned char dopname[256] PROGMEM =
 {
 /*00*/ I_BRK, I_ORA, I_XXX, I_XXX, I_TSB, I_ORA, I_ASL, I_XXX, I_PHP, I_ORA, I_ASL, I_XXX, I_TSB, I_ORA, I_ASL, I_XXX,
 /*10*/ I_BPL, I_ORA, I_ORA, I_XXX, I_TRB, I_ORA, I_ASL, I_XXX, I_CLC, I_ORA, I_INC, I_XXX, I_TRB, I_ORA, I_ASL, I_XXX,
@@ -166,7 +167,7 @@ unsigned char dopname[256] =
 /*F0*/ I_BEQ, I_SBC, I_SBC, I_XXX, I_XXX, I_SBC, I_INC, I_XXX, I_SED, I_SBC, I_PLX, I_XXX, I_XXX, I_SBC, I_INC, I_XXX
 };
 
-unsigned char dopaddr[256] =
+static const unsigned char dopaddr[256] PROGMEM =
 {
 /*00*/ IMP, INDX,  IMP, IMP,  ZP,   ZP,	   ZP,	 IMP,	IMP,  IMM,   IMPA,  IMP,  ABS,	  ABS,	 ABS,  IMP,
 /*10*/ BRA, INDY,  IND, IMP,  ZP,   ZPX,   ZPX,	 IMP,	IMP,  ABSY,  IMPA,  IMP,  ABS,	  ABSX,	 ABSX, IMP,
@@ -188,13 +189,20 @@ unsigned char dopaddr[256] =
 
 unsigned int disassemble(unsigned int addr)
 {
+  
 	unsigned int temp;
 	unsigned int op = readMemByteInc();
-        int mode = dopaddr[op];
+        int mode = pgm_read_byte(dopaddr + op);
 	unsigned int p1 = (mode > MARK2) ? readMemByteInc() : 0;
 	unsigned int p2 = (mode > MARK3) ? readMemByteInc() : 0;
 
-	log0("%04X : %s ", addr, opStrings[dopname[op]]);
+	int opIndex = pgm_read_byte(dopname + op) * 3;
+	log0("%04X : ", addr);
+	for (temp = 0; temp < 3; temp++) {
+	  log0("%c", pgm_read_byte(opString + opIndex + temp));
+	}
+	log0(" ");
+
 	switch (mode)
 	{
 	case IMP:

firmware/dis6809.c

@@ -15,6 +15,7 @@
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */
 
+#include <avr/pgmspace.h>
 #include "AtomBusMon.h"
 
 unsigned char get_memb(unsigned int addr) {
@@ -172,7 +173,7 @@ enum opcodes {
   OP_TSTB
 };
 
-static const char inst[] = "\
+static const char inst[] PROGMEM = "\
 --  \
 ??  \
 ABX \
@@ -319,7 +320,7 @@ TSTB";
 //	5 inherent
 //	6 relative
 
-unsigned char map0[] = {
+static const unsigned char map0[] = {
    OP_NEG , 0x22,
    OP_XX  , 0x22,
    OP_XX  , 0x12,
@@ -578,7 +579,7 @@ unsigned char map0[] = {
    OP_STU , 0x34,
 };
 
-unsigned char map1[] = {
+static const unsigned char map1[] = {
     33,	OP_LBRN, 0x46,
     34,	OP_LBHI, 0x46,
     35,	OP_LBLS, 0x46,
@@ -619,7 +620,7 @@ unsigned char map1[] = {
    255,	OP_STS , 0x44,
 };
 
-unsigned char map2[] = {
+static const unsigned char map2[] = {
     63,	OP_SWI3, 0x25,
    131,	OP_CMPU, 0x41,
    140,	OP_CMPS, 0x41,
@@ -700,7 +701,7 @@ unsigned int disassemble(unsigned int addr)
   int s, i;
   tt_u8 pb;
   char reg;
-  unsigned char *map = NULL;
+  const unsigned char *map = NULL;
 
   // Default for most undefined opcodes
   unsigned char sm = 0x10; // size_mode byte
@@ -748,8 +749,9 @@ unsigned int disassemble(unsigned int addr)
     fputs("   ", stream);
   }
 
+  const char *ip = inst + oi * 4; 
   for (i = 0; i < 4; i++)
-    fputc(inst[oi * 4 + i], stream);
+    fputc(pgm_read_byte(ip++), stream);
 
   fputs("  ", stream);
 

firmware/disz80.c

@@ -31,6 +31,8 @@ PERFORMANCE OF THIS SOFTWARE.
 */
 
 #include <string.h>
+#include <avr/pgmspace.h>
+
 #include "AtomBusMon.h"
 
 #define legal       0
@@ -94,208 +96,208 @@ char* word[] =
       "XH",     "XL",     "YH",     "YL",     "DIS(IX)","DIS(IY)"
   };
     
-unsigned char cmd_00[64][3] = 
+static const unsigned char cmd_00[192] PROGMEM = 
   {
-    {NOP,0,0},    
+    NOP,0,0,    
-    {LD,BC,NN},   
+    LD,BC,NN,   
-    {LD,XBC,A},   
+    LD,XBC,A,   
-    {INC,BC,0},   
+    INC,BC,0,   
-    {INC,B,0},    
+    INC,B,0,    
-    {DEC,B,0},    
+    DEC,B,0,    
-    {LD,B,N},     
+    LD,B,N,     
-    {RLCA,0,0},
+    RLCA,0,0,
-    {EX,AF,AF2},  
+    EX,AF,AF2,  
-    {ADD,HL,BC},  
+    ADD,HL,BC,  
-    {LD,A,XBC},   
+    LD,A,XBC,   
-    {DEC,BC,0},   
+    DEC,BC,0,   
-    {INC,C,0},    
+    INC,C,0,    
-    {DEC,C,0},    
+    DEC,C,0,    
-    {LD,C,N},     
+    LD,C,N,     
-    {RRCA,0,0},
+    RRCA,0,0,
-    {DJNZ,DIS,0}, 
+    DJNZ,DIS,0, 
-    {LD,DE,NN},   
+    LD,DE,NN,   
-    {LD,XDE,A},   
+    LD,XDE,A,   
-    {INC,DE,0},   
+    INC,DE,0,   
-    {INC,D,0},    
+    INC,D,0,    
-    {DEC,D,0},    
+    DEC,D,0,    
-    {LD,D,N},     
+    LD,D,N,     
-    {RLA,0,0},
+    RLA,0,0,
-    {JR,DIS,0},   
+    JR,DIS,0,   
-    {ADD,HL,DE},  
+    ADD,HL,DE,  
-    {LD,A,XDE},   
+    LD,A,XDE,   
-    {DEC,DE,0},   
+    DEC,DE,0,   
-    {INC,E,0},    
+    INC,E,0,    
-    {DEC,E,0},    
+    DEC,E,0,    
-    {LD,E,N},     
+    LD,E,N,     
-    {RRA,0,0},
+    RRA,0,0,
-    {JR,NZ,DIS},  
+    JR,NZ,DIS,  
-    {LD,HL,NN},   
+    LD,HL,NN,   
-    {LD,XNN,HL},  
+    LD,XNN,HL,  
-    {INC,HL,0},   
+    INC,HL,0,   
-    {INC,H,0},    
+    INC,H,0,    
-    {DEC,H,0},    
+    DEC,H,0,    
-    {LD,H,N},     
+    LD,H,N,     
-    {DAA,0,0},
+    DAA,0,0,
-    {JR,Z,DIS},   
+    JR,Z,DIS,   
-    {ADD,HL,HL},  
+    ADD,HL,HL,  
-    {LD,HL,XNN},  
+    LD,HL,XNN,  
-    {DEC,HL,0},   
+    DEC,HL,0,   
-    {INC,L,0},    
+    INC,L,0,    
-    {DEC,L,0},    
+    DEC,L,0,    
-    {LD,L,N},     
+    LD,L,N,     
-    {CPL,0,0},
+    CPL,0,0,
-    {JR,NC,DIS},  
+    JR,NC,DIS,  
-    {LD,SP,NN},   
+    LD,SP,NN,   
-    {LD,XNN,A},   
+    LD,XNN,A,   
-    {INC,SP,0},   
+    INC,SP,0,   
-    {INC,XHL,0},  
+    INC,XHL,0,  
-    {DEC,XHL,0},  
+    DEC,XHL,0,  
-    {LD,XHL,N},   
+    LD,XHL,N,   
-    {SCF,0,0},
+    SCF,0,0,
-    {JR,C,N},     
+    JR,C,N,     
-    {ADD,HL,SP},  
+    ADD,HL,SP,  
-    {LD,A,XNN},   
+    LD,A,XNN,   
-    {DEC,SP,0},   
+    DEC,SP,0,   
-    {INC,A,0},    
+    INC,A,0,    
-    {DEC,A,0},    
+    DEC,A,0,    
-    {LD,A,N},     
+    LD,A,N,     
-    {CCF,0,0}
+    CCF,0,0
   };
 
-unsigned char cmd_C0[64][3] = 
+static const unsigned char cmd_C0[192] PROGMEM = { 
-  {
-    {RET,NZ,0},   
-    {POP,BC,0},   
-    {JP,NZ,NN},   
-    {JP,NN,0},    
-    {CALL,NZ,NN}, 
-    {PUSH,BC,0},  
-    {ADD,A,N},    
-    {RST,N0,0},
-    {RET,Z,0},    
-    {RET,0,0},    
-    {JP,Z,NN},    
-    {PFX,CB,0},   
-    {CALL,Z,NN},  
-    {CALL,NN,0},  
-    {ADC,A,N},    
-    {RST,N1,0},
-    {RET,NC,0},   
-    {POP,DE,0},   
-    {JP,NC,NN},   
-    {OUT,XN,A},   
-    {CALL,NC,NN}, 
-    {PUSH,DE,0},  
-    {SUB,A,N},    
-    {RST,N2,0},
-    {RET,C,0},    
-    {EXX,0,0},    
-    {JP,C,NN},    
-    {IN,A,XN},    
-    {CALL,C,NN},  
-    {PFX,IX,0},   
-    {SBC,A,N},    
-    {RST,N3,0},
-    {RET,PO,0},   
-    {POP,HL,0},   
-    {JP,PO,NN},   
-    {EX,HL,XSP},  
-    {CALL,PO,NN}, 
-    {PUSH,HL,0},  
-    {AND,A,N},    
-    {RST,N4,0},
-    {RET,PE,0},   
-    {LD,PC,HL},   
-    {JP,PE,NN},   
-    {EX,DE,HL},   
-    {CALL,PE,NN}, 
-    {PFX,ED,0},   
-    {XOR,A,N},    
-    {RST,N5,0},
-    {RET,P,0},    
-    {POP,AF,0},   
-    {JP,P,NN},    
-    {DI,0,0},     
-    {CALL,P,NN},  
-    {PUSH,AF,0},  
-    {OR,A,N},     
-    {RST,N6,0},
-    {RET,M,0},    
-    {LD,SP,HL},   
-    {JP,M,NN},    
-    {EI,0,0},     
-    {CALL,M,NN},  
-    {PFX,IY,0},   
-    {CP,A,N},     
-    {RST,N7,0}
-  };
   
-unsigned char cmd_ED40[64][3] = 
+    RET,NZ,0,   
-  {
+    POP,BC,0,   
-    {IN,B,XC},    
+    JP,NZ,NN,   
-    {OUT,XC,B},   
+    JP,NN,0,    
-    {SBC,HL,BC},  
+    CALL,NZ,NN, 
-    {LD,XNN,BC},  
+    PUSH,BC,0,  
-    {NEG,0,0},    
+    ADD,A,N,    
-    {RETN,0,0},   
+    RST,N0,0,
-    {IM,N0,0},    
+    RET,Z,0,    
-    {LD,I,A},
+    RET,0,0,    
-    {IN,C,XC},    
+    JP,Z,NN,    
-    {OUT,XC,C},   
+    PFX,CB,0,   
-    {ADC,HL,BC},  
+    CALL,Z,NN,  
-    {LD,BC,XNN},  
+    CALL,NN,0,  
-    {NEG,0,0},    
+    ADC,A,N,    
-    {RETI,0,0},   
+    RST,N1,0,
-    {IM,N0,0},    
+    RET,NC,0,   
-    {LD,R,A},
+    POP,DE,0,   
-    {IN,D,XC},    
+    JP,NC,NN,   
-    {OUT,XC,D},   
+    OUT,XN,A,   
-    {SBC,HL,DE},  
+    CALL,NC,NN, 
-    {LD,XNN,DE},  
+    PUSH,DE,0,  
-    {NEG,0,0},    
+    SUB,A,N,    
-    {RETN,0,0},   
+    RST,N2,0,
-    {IM,N1,0},    
+    RET,C,0,    
-    {LD,A,I},
+    EXX,0,0,    
-    {IN,E,XC},    
+    JP,C,NN,    
-    {OUT,XC,E},   
+    IN,A,XN,    
-    {ADC,HL,DE},  
+    CALL,C,NN,  
-    {LD,DE,XNN},  
+    PFX,IX,0,   
-    {NEG,0,0},    
+    SBC,A,N,    
-    {RETI,0,0},   
+    RST,N3,0,
-    {IM,N2,0},    
+    RET,PO,0,   
-    {LD,A,R},
+    POP,HL,0,   
-    {IN,H,XC},    
+    JP,PO,NN,   
-    {OUT,XC,H},   
+    EX,HL,XSP,  
-    {SBC,HL,HL},  
+    CALL,PO,NN, 
-    {LD,XNN,HL},  
+    PUSH,HL,0,  
-    {NEG,0,0},    
+    AND,A,N,    
-    {RETN,0,0},   
+    RST,N4,0,
-    {IM,N0,0},    
+    RET,PE,0,   
-    {RRD,0,0},
+    LD,PC,HL,   
-    {IN,L,XC},    
+    JP,PE,NN,   
-    {OUT,XC,L},   
+    EX,DE,HL,   
-    {ADC,HL,HL},  
+    CALL,PE,NN, 
-    {LD,HL,XNN},  
+    PFX,ED,0,   
-    {NEG,0,0},    
+    XOR,A,N,    
-    {RETI,0,0},   
+    RST,N5,0,
-    {IM,N0,0},    
+    RET,P,0,    
-    {RLD,0,0},
+    POP,AF,0,   
-    {IN,F,XC},    
+    JP,P,NN,    
-    {OUT,XC,N0},  
+    DI,0,0,     
-    {SBC,HL,SP},  
+    CALL,P,NN,  
-    {LD,XNN,SP},  
+    PUSH,AF,0,  
-    {NEG,0,0},    
+    OR,A,N,     
-    {RETN,0,0},   
+    RST,N6,0,
-    {IM,N1,0},    
+    RET,M,0,    
-    {NOP,0,0},
+    LD,SP,HL,   
-    {IN,A,XC},    
+    JP,M,NN,    
-    {OUT,XC,A},   
+    EI,0,0,     
-    {ADC,HL,SP},  
+    CALL,M,NN,  
-    {LD,SP,XNN},  
+    PFX,IY,0,   
-    {NEG,0,0},    
+    CP,A,N,     
-    {RETI,0,0},   
+    RST,N7,0
-    {IM,N2,0},    
+};
-    {NOP,0,0} 
+
+static const unsigned char cmd_ED40[192] PROGMEM = {
+  
+    IN,B,XC,    
+    OUT,XC,B,   
+    SBC,HL,BC,  
+    LD,XNN,BC,  
+    NEG,0,0,    
+    RETN,0,0,   
+    IM,N0,0,    
+    LD,I,A,
+    IN,C,XC,    
+    OUT,XC,C,   
+    ADC,HL,BC,  
+    LD,BC,XNN,  
+    NEG,0,0,    
+    RETI,0,0,   
+    IM,N0,0,    
+    LD,R,A,
+    IN,D,XC,    
+    OUT,XC,D,   
+    SBC,HL,DE,  
+    LD,XNN,DE,  
+    NEG,0,0,    
+    RETN,0,0,   
+    IM,N1,0,    
+    LD,A,I,
+    IN,E,XC,    
+    OUT,XC,E,   
+    ADC,HL,DE,  
+    LD,DE,XNN,  
+    NEG,0,0,    
+    RETI,0,0,   
+    IM,N2,0,    
+    LD,A,R,
+    IN,H,XC,    
+    OUT,XC,H,   
+    SBC,HL,HL,  
+    LD,XNN,HL,  
+    NEG,0,0,    
+    RETN,0,0,   
+    IM,N0,0,    
+    RRD,0,0,
+    IN,L,XC,    
+    OUT,XC,L,   
+    ADC,HL,HL,  
+    LD,HL,XNN,  
+    NEG,0,0,    
+    RETI,0,0,   
+    IM,N0,0,    
+    RLD,0,0,
+    IN,F,XC,    
+    OUT,XC,N0,  
+    SBC,HL,SP,  
+    LD,XNN,SP,  
+    NEG,0,0,    
+    RETN,0,0,   
+    IM,N1,0,    
+    NOP,0,0,
+    IN,A,XC,    
+    OUT,XC,A,   
+    ADC,HL,SP,  
+    LD,SP,XNN,  
+    NEG,0,0,    
+    RETI,0,0,   
+    IM,N2,0,    
+    NOP,0,0 
   };
 
 unsigned char cmd_halt[] = { HALT,0,0 };
@@ -317,15 +319,24 @@ unsigned char Peek(unsigned int addr) {
   return readMemByte();
 }
 
+const unsigned char *copyFromPgmMem(const unsigned char *mem) {
+  static unsigned char buffer[3];
+  buffer[0] = pgm_read_byte(mem++);
+  buffer[1] = pgm_read_byte(mem++);
+  buffer[2] = pgm_read_byte(mem++);
+  return buffer;
+}
+
+
 // ---- return mnenonic descriptor for normal instructions
 //      note: for immediate use only, returned result becomes invalid with next call!
-unsigned char* mnemo(unsigned char op) {
+const unsigned char* mnemo(unsigned char op) {
   static unsigned char cl[3]={LD,A,A};
   static unsigned char ca[3]={ADD,A,A};
 
   switch (op>>6)
     {
-    case 0: return cmd_00[op];
+    case 0: return copyFromPgmMem(cmd_00 + op * 3);
     case 1: if (op==0x76) return cmd_halt;
       cl[1] = B + ((op>>3)&0x07); 
       cl[2] = B + (op&0x07); 
@@ -333,7 +344,7 @@ unsigned char* mnemo(unsigned char op) {
     case 2: ca[0] = c_ari[(op>>3)&0x07];
       ca[2] = B + (op&0x07); 
       return ca;
-    case 3: return cmd_C0[op&0x3f];
+    case 3: return copyFromPgmMem(cmd_C0 + (op&0x3f) * 3);
     }
   return NULL;
 }
@@ -386,7 +397,7 @@ unsigned char* mnemoIYCB(unsigned char op) {
 
 // ---- return mnenonic descriptor for ED instructions
 //      note: for immediate use only!
-unsigned char* mnemoED(unsigned char op) {
+const unsigned char* mnemoED(unsigned char op) {
   static unsigned char cmd[3]={0,0,0};
 
   if (op<0x40) return cmd_nop;
@@ -397,7 +408,7 @@ unsigned char* mnemoED(unsigned char op) {
       return cmd;
     };
     
-  return cmd_ED40[op-0x40];   
+  return copyFromPgmMem(cmd_ED40 + (op-0x40) * 3);   
 }
 
 
@@ -471,7 +482,7 @@ int IllegalED (unsigned char op) {
 //      all illegal instructions, which don't use XH or XL are weird
 //      prefixes are legal
 int IllegalXX (unsigned char op) {
-  unsigned char *c;
+  const unsigned char *c;
     
   c = mnemo(op);
 
@@ -569,7 +580,7 @@ void xword (unsigned char n, unsigned int *ip) {
 
 
 // ---- expand 3-char descriptor m[3] to mnemonic with arguments via pc
-void disass (unsigned char *m, unsigned int *ip) {
+void disass (const unsigned char *m, unsigned int *ip) {
   log0("%-5s", word[*m++]);
   if (*m) {
     xword(*m++,ip);

src/AVR8/CommonPacks/SynthCtrlPack.vhd

@@ -13,8 +13,8 @@ package SynthCtrlPack is
 
 -- Please note: Do not change these settings, this is not quite ready yet. Jack Gassett
 -- Control the size of Program and Data memory.
-constant CDATAMEMSIZE	: integer := 11;			--2^(x+1)=Data SRAM Memory Size   	(10=2048) (Default 11=4096) (12=8192)
+constant CDATAMEMSIZE	: integer := 10;			--2^(x+1)=Data SRAM Memory Size   	(10=2048) (Default 11=4096) (12=8192)
-constant CPROGMEMSIZE	: integer := 12;		--(2^(x+1))*2)=Program Memory Size	(10=4096) (11=8192) (Default 12=16384)
+constant CPROGMEMSIZE	: integer := 13;		--(2^(x+1))*2)=Program Memory Size	(10=4096) (11=8192) (Default 12=16384)
 -- Calculate at Wolfram Alpha (http://www.wolframalpha.com/input/?i=%282^%28x%2B1%29%29*2%29%2Cx%3D12)
 
 -- Reset generator

src/AVR8/Memory/XDM2Kx8.vhd

@@ -0,0 +1,66 @@
+--************************************************************************************************
+-- 2Kx8(16 KB) DM RAM for AVR Core(Xilinx)
+-- Version 0.2
+-- Designed by Ruslan Lepetenok 
+-- Jack Gassett for use with Papilio
+-- Modified 30.07.2005
+--************************************************************************************************
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use WORK.SynthCtrlPack.all; -- Synthesis control
+
+-- For Synplicity Synplify
+--library virtexe;
+--use	virtexe.components.all; 
+
+-- Aldec
+library	unisim;
+use unisim.vcomponents.all;
+
+entity XDM2Kx8 is port(
+	                    cp2       : in  std_logic;
+						ce        : in  std_logic; 
+	                    address   : in  std_logic_vector(CDATAMEMSIZE downto 0); 
+					    din       : in  std_logic_vector(7 downto 0);		                
+					    dout      : out std_logic_vector(7 downto 0);
+					    we        : in  std_logic
+					   );
+end XDM2Kx8;
+
+architecture RTL of XDM2Kx8 is
+
+signal RAMBlDOut     : std_logic_vector(dout'range);
+
+signal WEB      : std_logic;
+signal cp2n     : std_logic;
+signal gnd      : std_logic;
+
+signal DIP : STD_LOGIC_VECTOR(0 downto 0) := "1";
+
+signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
+
+begin
+
+gnd  <= '0';	
+
+WEB <= '1' when we='1' else '0';
+
+
+RAM_Byte:component RAMB16_S9 port map(
+                                      DO   => RAMBlDOut(7 downto 0),
+                                      ADDR => address(10 downto 0),
+                                      DI   => din(7 downto 0),
+												  DIP  => DIP,
+                                      EN   => ce,
+									  SSR  => SSR,
+                                      CLK  => cp2,
+                                      WE   => WEB
+                                      );
+
+-- Output data mux
+dout <= RAMBlDOut;
+
+end RTL;

src/AVR8/Memory/XPM9Kx16.vhd

@@ -0,0 +1,826 @@
+--************************************************************************************************
+-- 8Kx16(8 KB) PM RAM for AVR Core(Xilinx)
+-- Version 0.1
+-- Designed by Ruslan Lepetenok 
+-- Modified by Jack Gassett for use with Papilio
+-- Modified 11.06.2009
+--************************************************************************************************
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use WORK.SynthCtrlPack.all; -- Synthesis control
+use WORK.prog_mem_init_pkg.all; -- Init file for program memory.
+
+-- For Synplicity Synplify
+--library virtexe;
+--use	virtexe.components.all; 
+
+-- Aldec
+library	unisim;
+use unisim.vcomponents.all;
+
+entity XPM9Kx16 is port(
+	                  cp2     : in  std_logic;
+					  ce      : in  std_logic; 
+	                  address : in  std_logic_vector(13 downto 0); 
+					  din     : in  std_logic_vector(15 downto 0);		                
+					  dout    : out std_logic_vector(15 downto 0);
+					  we     : in  std_logic
+					  );
+end XPM9Kx16;
+
+architecture RTL of XPM9Kx16 is
+
+type   RAMBlDOut_Type is array(2**(address'length-10)-1 downto 0) of  std_logic_vector(dout'range);
+signal RAMBlDOut     : RAMBlDOut_Type;
+
+signal WEB     : std_logic_vector(2**(address'length-10)-1 downto 0);
+signal gnd      : std_logic;
+signal DIP : STD_LOGIC_VECTOR(1 downto 0) := "11";
+signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
+
+
+begin
+
+gnd <= '0';	
+
+WEB_Dcd:for i in WEB'range generate 
+ WEB(i) <= '1' when (we='1' and address(address'high downto 10)=i) else '0';
+end generate ;
+
+
+--RAM_Inst:for i in 0 to 2**(address'length-10)-1 generate
+
+RAM_Word0:component RAMB16_S18 
+generic map (
+INIT => X"00000", -- Value of output RAM registers at startup
+SRVAL => X"00000", -- Ouput value upon SSR assertion
+WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+-- The following INIT_xx declarations specify the intial contents of the RAM
+-- Address 0 to 255
+INIT_00 => PM_Inst_RAM_Word0_INIT_00,
+INIT_01 => PM_Inst_RAM_Word0_INIT_01,
+INIT_02 => PM_Inst_RAM_Word0_INIT_02,
+INIT_03 => PM_Inst_RAM_Word0_INIT_03,
+INIT_04 => PM_Inst_RAM_Word0_INIT_04,
+INIT_05 => PM_Inst_RAM_Word0_INIT_05,
+INIT_06 => PM_Inst_RAM_Word0_INIT_06,
+INIT_07 => PM_Inst_RAM_Word0_INIT_07,
+INIT_08 => PM_Inst_RAM_Word0_INIT_08,
+INIT_09 => PM_Inst_RAM_Word0_INIT_09,
+INIT_0A => PM_Inst_RAM_Word0_INIT_0A,
+INIT_0B => PM_Inst_RAM_Word0_INIT_0B,
+INIT_0C => PM_Inst_RAM_Word0_INIT_0C,
+INIT_0D => PM_Inst_RAM_Word0_INIT_0D,
+INIT_0E => PM_Inst_RAM_Word0_INIT_0E,
+INIT_0F => PM_Inst_RAM_Word0_INIT_0F,
+INIT_10 => PM_Inst_RAM_Word0_INIT_10,
+INIT_11 => PM_Inst_RAM_Word0_INIT_11,
+INIT_12 => PM_Inst_RAM_Word0_INIT_12,
+INIT_13 => PM_Inst_RAM_Word0_INIT_13,
+INIT_14 => PM_Inst_RAM_Word0_INIT_14,
+INIT_15 => PM_Inst_RAM_Word0_INIT_15,
+INIT_16 => PM_Inst_RAM_Word0_INIT_16,
+INIT_17 => PM_Inst_RAM_Word0_INIT_17,
+INIT_18 => PM_Inst_RAM_Word0_INIT_18,
+INIT_19 => PM_Inst_RAM_Word0_INIT_19,
+INIT_1A => PM_Inst_RAM_Word0_INIT_1A,
+INIT_1B => PM_Inst_RAM_Word0_INIT_1B,
+INIT_1C => PM_Inst_RAM_Word0_INIT_1C,
+INIT_1D => PM_Inst_RAM_Word0_INIT_1D,
+INIT_1E => PM_Inst_RAM_Word0_INIT_1E,
+INIT_1F => PM_Inst_RAM_Word0_INIT_1F,
+INIT_20 => PM_Inst_RAM_Word0_INIT_20,
+INIT_21 => PM_Inst_RAM_Word0_INIT_21,
+INIT_22 => PM_Inst_RAM_Word0_INIT_22,
+INIT_23 => PM_Inst_RAM_Word0_INIT_23,
+INIT_24 => PM_Inst_RAM_Word0_INIT_24,
+INIT_25 => PM_Inst_RAM_Word0_INIT_25,
+INIT_26 => PM_Inst_RAM_Word0_INIT_26,
+INIT_27 => PM_Inst_RAM_Word0_INIT_27,
+INIT_28 => PM_Inst_RAM_Word0_INIT_28,
+INIT_29 => PM_Inst_RAM_Word0_INIT_29,
+INIT_2A => PM_Inst_RAM_Word0_INIT_2A,
+INIT_2B => PM_Inst_RAM_Word0_INIT_2B,
+INIT_2C => PM_Inst_RAM_Word0_INIT_2C,
+INIT_2D => PM_Inst_RAM_Word0_INIT_2D,
+INIT_2E => PM_Inst_RAM_Word0_INIT_2E,
+INIT_2F => PM_Inst_RAM_Word0_INIT_2F,
+-- Address 768 to 1023
+INIT_30 => PM_Inst_RAM_Word0_INIT_30,
+INIT_31 => PM_Inst_RAM_Word0_INIT_31,
+INIT_32 => PM_Inst_RAM_Word0_INIT_32,
+INIT_33 => PM_Inst_RAM_Word0_INIT_33,
+INIT_34 => PM_Inst_RAM_Word0_INIT_34,
+INIT_35 => PM_Inst_RAM_Word0_INIT_35,
+INIT_36 => PM_Inst_RAM_Word0_INIT_36,
+INIT_37 => PM_Inst_RAM_Word0_INIT_37,
+INIT_38 => PM_Inst_RAM_Word0_INIT_38,
+INIT_39 => PM_Inst_RAM_Word0_INIT_39,
+INIT_3A => PM_Inst_RAM_Word0_INIT_3A,
+INIT_3B => PM_Inst_RAM_Word0_INIT_3B,
+INIT_3C => PM_Inst_RAM_Word0_INIT_3C,
+INIT_3D => PM_Inst_RAM_Word0_INIT_3D,
+INIT_3E => PM_Inst_RAM_Word0_INIT_3E,
+INIT_3F => PM_Inst_RAM_Word0_INIT_3F
+)
+port map(
+                                      DO   => RAMBlDOut(0)(15 downto 0),
+                                      ADDR => address(9 downto 0),
+                                      DI   => din(15 downto 0),
+												  DIP  => DIP,
+                                      EN   => ce,
+												  SSR  => SSR,
+                                      CLK  => cp2,
+                                      WE   => WEB(0)
+                                      );
+												  
+RAM_Word1:component RAMB16_S18 
+generic map (
+INIT => X"00000", -- Value of output RAM registers at startup
+SRVAL => X"00000", -- Ouput value upon SSR assertion
+WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+-- The following INIT_xx declarations specify the intial contents of the RAM
+-- Address 0 to 255
+INIT_00 => PM_Inst_RAM_Word1_INIT_00,
+INIT_01 => PM_Inst_RAM_Word1_INIT_01,
+INIT_02 => PM_Inst_RAM_Word1_INIT_02,
+INIT_03 => PM_Inst_RAM_Word1_INIT_03,
+INIT_04 => PM_Inst_RAM_Word1_INIT_04,
+INIT_05 => PM_Inst_RAM_Word1_INIT_05,
+INIT_06 => PM_Inst_RAM_Word1_INIT_06,
+INIT_07 => PM_Inst_RAM_Word1_INIT_07,
+INIT_08 => PM_Inst_RAM_Word1_INIT_08,
+INIT_09 => PM_Inst_RAM_Word1_INIT_09,
+INIT_0A => PM_Inst_RAM_Word1_INIT_0A,
+INIT_0B => PM_Inst_RAM_Word1_INIT_0B,
+INIT_0C => PM_Inst_RAM_Word1_INIT_0C,
+INIT_0D => PM_Inst_RAM_Word1_INIT_0D,
+INIT_0E => PM_Inst_RAM_Word1_INIT_0E,
+INIT_0F => PM_Inst_RAM_Word1_INIT_0F,
+INIT_10 => PM_Inst_RAM_Word1_INIT_10,
+INIT_11 => PM_Inst_RAM_Word1_INIT_11,
+INIT_12 => PM_Inst_RAM_Word1_INIT_12,
+INIT_13 => PM_Inst_RAM_Word1_INIT_13,
+INIT_14 => PM_Inst_RAM_Word1_INIT_14,
+INIT_15 => PM_Inst_RAM_Word1_INIT_15,
+INIT_16 => PM_Inst_RAM_Word1_INIT_16,
+INIT_17 => PM_Inst_RAM_Word1_INIT_17,
+INIT_18 => PM_Inst_RAM_Word1_INIT_18,
+INIT_19 => PM_Inst_RAM_Word1_INIT_19,
+INIT_1A => PM_Inst_RAM_Word1_INIT_1A,
+INIT_1B => PM_Inst_RAM_Word1_INIT_1B,
+INIT_1C => PM_Inst_RAM_Word1_INIT_1C,
+INIT_1D => PM_Inst_RAM_Word1_INIT_1D,
+INIT_1E => PM_Inst_RAM_Word1_INIT_1E,
+INIT_1F => PM_Inst_RAM_Word1_INIT_1F,
+INIT_20 => PM_Inst_RAM_Word1_INIT_20,
+INIT_21 => PM_Inst_RAM_Word1_INIT_21,
+INIT_22 => PM_Inst_RAM_Word1_INIT_22,
+INIT_23 => PM_Inst_RAM_Word1_INIT_23,
+INIT_24 => PM_Inst_RAM_Word1_INIT_24,
+INIT_25 => PM_Inst_RAM_Word1_INIT_25,
+INIT_26 => PM_Inst_RAM_Word1_INIT_26,
+INIT_27 => PM_Inst_RAM_Word1_INIT_27,
+INIT_28 => PM_Inst_RAM_Word1_INIT_28,
+INIT_29 => PM_Inst_RAM_Word1_INIT_29,
+INIT_2A => PM_Inst_RAM_Word1_INIT_2A,
+INIT_2B => PM_Inst_RAM_Word1_INIT_2B,
+INIT_2C => PM_Inst_RAM_Word1_INIT_2C,
+INIT_2D => PM_Inst_RAM_Word1_INIT_2D,
+INIT_2E => PM_Inst_RAM_Word1_INIT_2E,
+INIT_2F => PM_Inst_RAM_Word1_INIT_2F,
+-- Address 768 to 1023
+INIT_30 => PM_Inst_RAM_Word1_INIT_30,
+INIT_31 => PM_Inst_RAM_Word1_INIT_31,
+INIT_32 => PM_Inst_RAM_Word1_INIT_32,
+INIT_33 => PM_Inst_RAM_Word1_INIT_33,
+INIT_34 => PM_Inst_RAM_Word1_INIT_34,
+INIT_35 => PM_Inst_RAM_Word1_INIT_35,
+INIT_36 => PM_Inst_RAM_Word1_INIT_36,
+INIT_37 => PM_Inst_RAM_Word1_INIT_37,
+INIT_38 => PM_Inst_RAM_Word1_INIT_38,
+INIT_39 => PM_Inst_RAM_Word1_INIT_39,
+INIT_3A => PM_Inst_RAM_Word1_INIT_3A,
+INIT_3B => PM_Inst_RAM_Word1_INIT_3B,
+INIT_3C => PM_Inst_RAM_Word1_INIT_3C,
+INIT_3D => PM_Inst_RAM_Word1_INIT_3D,
+INIT_3E => PM_Inst_RAM_Word1_INIT_3E,
+INIT_3F => PM_Inst_RAM_Word1_INIT_3F
+)
+port map(
+                                      DO   => RAMBlDOut(1)(15 downto 0),
+                                      ADDR => address(9 downto 0),
+                                      DI   => din(15 downto 0),
+												  DIP  => DIP,
+                                      EN   => ce,
+												  SSR  => SSR,
+                                      CLK  => cp2,
+                                      WE   => WEB(1)
+                                      );
+
+RAM_Word2:component RAMB16_S18 
+generic map (
+INIT => X"00000", -- Value of output RAM registers at startup
+SRVAL => X"00000", -- Ouput value upon SSR assertion
+WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+-- The following INIT_xx declarations specify the intial contents of the RAM
+-- Address 0 to 255
+INIT_00 => PM_Inst_RAM_Word2_INIT_00,
+INIT_01 => PM_Inst_RAM_Word2_INIT_01,
+INIT_02 => PM_Inst_RAM_Word2_INIT_02,
+INIT_03 => PM_Inst_RAM_Word2_INIT_03,
+INIT_04 => PM_Inst_RAM_Word2_INIT_04,
+INIT_05 => PM_Inst_RAM_Word2_INIT_05,
+INIT_06 => PM_Inst_RAM_Word2_INIT_06,
+INIT_07 => PM_Inst_RAM_Word2_INIT_07,
+INIT_08 => PM_Inst_RAM_Word2_INIT_08,
+INIT_09 => PM_Inst_RAM_Word2_INIT_09,
+INIT_0A => PM_Inst_RAM_Word2_INIT_0A,
+INIT_0B => PM_Inst_RAM_Word2_INIT_0B,
+INIT_0C => PM_Inst_RAM_Word2_INIT_0C,
+INIT_0D => PM_Inst_RAM_Word2_INIT_0D,
+INIT_0E => PM_Inst_RAM_Word2_INIT_0E,
+INIT_0F => PM_Inst_RAM_Word2_INIT_0F,
+INIT_10 => PM_Inst_RAM_Word2_INIT_10,
+INIT_11 => PM_Inst_RAM_Word2_INIT_11,
+INIT_12 => PM_Inst_RAM_Word2_INIT_12,
+INIT_13 => PM_Inst_RAM_Word2_INIT_13,
+INIT_14 => PM_Inst_RAM_Word2_INIT_14,
+INIT_15 => PM_Inst_RAM_Word2_INIT_15,
+INIT_16 => PM_Inst_RAM_Word2_INIT_16,
+INIT_17 => PM_Inst_RAM_Word2_INIT_17,
+INIT_18 => PM_Inst_RAM_Word2_INIT_18,
+INIT_19 => PM_Inst_RAM_Word2_INIT_19,
+INIT_1A => PM_Inst_RAM_Word2_INIT_1A,
+INIT_1B => PM_Inst_RAM_Word2_INIT_1B,
+INIT_1C => PM_Inst_RAM_Word2_INIT_1C,
+INIT_1D => PM_Inst_RAM_Word2_INIT_1D,
+INIT_1E => PM_Inst_RAM_Word2_INIT_1E,
+INIT_1F => PM_Inst_RAM_Word2_INIT_1F,
+INIT_20 => PM_Inst_RAM_Word2_INIT_20,
+INIT_21 => PM_Inst_RAM_Word2_INIT_21,
+INIT_22 => PM_Inst_RAM_Word2_INIT_22,
+INIT_23 => PM_Inst_RAM_Word2_INIT_23,
+INIT_24 => PM_Inst_RAM_Word2_INIT_24,
+INIT_25 => PM_Inst_RAM_Word2_INIT_25,
+INIT_26 => PM_Inst_RAM_Word2_INIT_26,
+INIT_27 => PM_Inst_RAM_Word2_INIT_27,
+INIT_28 => PM_Inst_RAM_Word2_INIT_28,
+INIT_29 => PM_Inst_RAM_Word2_INIT_29,
+INIT_2A => PM_Inst_RAM_Word2_INIT_2A,
+INIT_2B => PM_Inst_RAM_Word2_INIT_2B,
+INIT_2C => PM_Inst_RAM_Word2_INIT_2C,
+INIT_2D => PM_Inst_RAM_Word2_INIT_2D,
+INIT_2E => PM_Inst_RAM_Word2_INIT_2E,
+INIT_2F => PM_Inst_RAM_Word2_INIT_2F,
+-- Address 768 to 1023
+INIT_30 => PM_Inst_RAM_Word2_INIT_30,
+INIT_31 => PM_Inst_RAM_Word2_INIT_31,
+INIT_32 => PM_Inst_RAM_Word2_INIT_32,
+INIT_33 => PM_Inst_RAM_Word2_INIT_33,
+INIT_34 => PM_Inst_RAM_Word2_INIT_34,
+INIT_35 => PM_Inst_RAM_Word2_INIT_35,
+INIT_36 => PM_Inst_RAM_Word2_INIT_36,
+INIT_37 => PM_Inst_RAM_Word2_INIT_37,
+INIT_38 => PM_Inst_RAM_Word2_INIT_38,
+INIT_39 => PM_Inst_RAM_Word2_INIT_39,
+INIT_3A => PM_Inst_RAM_Word2_INIT_3A,
+INIT_3B => PM_Inst_RAM_Word2_INIT_3B,
+INIT_3C => PM_Inst_RAM_Word2_INIT_3C,
+INIT_3D => PM_Inst_RAM_Word2_INIT_3D,
+INIT_3E => PM_Inst_RAM_Word2_INIT_3E,
+INIT_3F => PM_Inst_RAM_Word2_INIT_3F
+)
+port map(
+                                      DO   => RAMBlDOut(2)(15 downto 0),
+                                      ADDR => address(9 downto 0),
+                                      DI   => din(15 downto 0),
+												  DIP  => DIP,
+                                      EN   => ce,
+												  SSR  => SSR,
+                                      CLK  => cp2,
+                                      WE   => WEB(2)
+                                      );
+
+RAM_Word3:component RAMB16_S18 
+generic map (
+INIT => X"00000", -- Value of output RAM registers at startup
+SRVAL => X"00000", -- Ouput value upon SSR assertion
+WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+-- The following INIT_xx declarations specify the intial contents of the RAM
+-- Address 0 to 255
+INIT_00 => PM_Inst_RAM_Word3_INIT_00,
+INIT_01 => PM_Inst_RAM_Word3_INIT_01,
+INIT_02 => PM_Inst_RAM_Word3_INIT_02,
+INIT_03 => PM_Inst_RAM_Word3_INIT_03,
+INIT_04 => PM_Inst_RAM_Word3_INIT_04,
+INIT_05 => PM_Inst_RAM_Word3_INIT_05,
+INIT_06 => PM_Inst_RAM_Word3_INIT_06,
+INIT_07 => PM_Inst_RAM_Word3_INIT_07,
+INIT_08 => PM_Inst_RAM_Word3_INIT_08,
+INIT_09 => PM_Inst_RAM_Word3_INIT_09,
+INIT_0A => PM_Inst_RAM_Word3_INIT_0A,
+INIT_0B => PM_Inst_RAM_Word3_INIT_0B,
+INIT_0C => PM_Inst_RAM_Word3_INIT_0C,
+INIT_0D => PM_Inst_RAM_Word3_INIT_0D,
+INIT_0E => PM_Inst_RAM_Word3_INIT_0E,
+INIT_0F => PM_Inst_RAM_Word3_INIT_0F,
+INIT_10 => PM_Inst_RAM_Word3_INIT_10,
+INIT_11 => PM_Inst_RAM_Word3_INIT_11,
+INIT_12 => PM_Inst_RAM_Word3_INIT_12,
+INIT_13 => PM_Inst_RAM_Word3_INIT_13,
+INIT_14 => PM_Inst_RAM_Word3_INIT_14,
+INIT_15 => PM_Inst_RAM_Word3_INIT_15,
+INIT_16 => PM_Inst_RAM_Word3_INIT_16,
+INIT_17 => PM_Inst_RAM_Word3_INIT_17,
+INIT_18 => PM_Inst_RAM_Word3_INIT_18,
+INIT_19 => PM_Inst_RAM_Word3_INIT_19,
+INIT_1A => PM_Inst_RAM_Word3_INIT_1A,
+INIT_1B => PM_Inst_RAM_Word3_INIT_1B,
+INIT_1C => PM_Inst_RAM_Word3_INIT_1C,
+INIT_1D => PM_Inst_RAM_Word3_INIT_1D,
+INIT_1E => PM_Inst_RAM_Word3_INIT_1E,
+INIT_1F => PM_Inst_RAM_Word3_INIT_1F,
+INIT_20 => PM_Inst_RAM_Word3_INIT_20,
+INIT_21 => PM_Inst_RAM_Word3_INIT_21,
+INIT_22 => PM_Inst_RAM_Word3_INIT_22,
+INIT_23 => PM_Inst_RAM_Word3_INIT_23,
+INIT_24 => PM_Inst_RAM_Word3_INIT_24,
+INIT_25 => PM_Inst_RAM_Word3_INIT_25,
+INIT_26 => PM_Inst_RAM_Word3_INIT_26,
+INIT_27 => PM_Inst_RAM_Word3_INIT_27,
+INIT_28 => PM_Inst_RAM_Word3_INIT_28,
+INIT_29 => PM_Inst_RAM_Word3_INIT_29,
+INIT_2A => PM_Inst_RAM_Word3_INIT_2A,
+INIT_2B => PM_Inst_RAM_Word3_INIT_2B,
+INIT_2C => PM_Inst_RAM_Word3_INIT_2C,
+INIT_2D => PM_Inst_RAM_Word3_INIT_2D,
+INIT_2E => PM_Inst_RAM_Word3_INIT_2E,
+INIT_2F => PM_Inst_RAM_Word3_INIT_2F,
+-- Address 768 to 1023
+INIT_30 => PM_Inst_RAM_Word3_INIT_30,
+INIT_31 => PM_Inst_RAM_Word3_INIT_31,
+INIT_32 => PM_Inst_RAM_Word3_INIT_32,
+INIT_33 => PM_Inst_RAM_Word3_INIT_33,
+INIT_34 => PM_Inst_RAM_Word3_INIT_34,
+INIT_35 => PM_Inst_RAM_Word3_INIT_35,
+INIT_36 => PM_Inst_RAM_Word3_INIT_36,
+INIT_37 => PM_Inst_RAM_Word3_INIT_37,
+INIT_38 => PM_Inst_RAM_Word3_INIT_38,
+INIT_39 => PM_Inst_RAM_Word3_INIT_39,
+INIT_3A => PM_Inst_RAM_Word3_INIT_3A,
+INIT_3B => PM_Inst_RAM_Word3_INIT_3B,
+INIT_3C => PM_Inst_RAM_Word3_INIT_3C,
+INIT_3D => PM_Inst_RAM_Word3_INIT_3D,
+INIT_3E => PM_Inst_RAM_Word3_INIT_3E,
+INIT_3F => PM_Inst_RAM_Word3_INIT_3F
+)
+port map(
+                                      DO   => RAMBlDOut(3)(15 downto 0),
+                                      ADDR => address(9 downto 0),
+                                      DI   => din(15 downto 0),
+												  DIP  => DIP,
+                                      EN   => ce,
+												  SSR  => SSR,
+                                      CLK  => cp2,
+                                      WE   => WEB(3)
+                                      );
+
+RAM_Word4:component RAMB16_S18 
+generic map (
+INIT => X"00000", -- Value of output RAM registers at startup
+SRVAL => X"00000", -- Ouput value upon SSR assertion
+WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+-- The following INIT_xx declarations specify the intial contents of the RAM
+-- Address 0 to 255
+INIT_00 => PM_Inst_RAM_Word4_INIT_00,
+INIT_01 => PM_Inst_RAM_Word4_INIT_01,
+INIT_02 => PM_Inst_RAM_Word4_INIT_02,
+INIT_03 => PM_Inst_RAM_Word4_INIT_03,
+INIT_04 => PM_Inst_RAM_Word4_INIT_04,
+INIT_05 => PM_Inst_RAM_Word4_INIT_05,
+INIT_06 => PM_Inst_RAM_Word4_INIT_06,
+INIT_07 => PM_Inst_RAM_Word4_INIT_07,
+INIT_08 => PM_Inst_RAM_Word4_INIT_08,
+INIT_09 => PM_Inst_RAM_Word4_INIT_09,
+INIT_0A => PM_Inst_RAM_Word4_INIT_0A,
+INIT_0B => PM_Inst_RAM_Word4_INIT_0B,
+INIT_0C => PM_Inst_RAM_Word4_INIT_0C,
+INIT_0D => PM_Inst_RAM_Word4_INIT_0D,
+INIT_0E => PM_Inst_RAM_Word4_INIT_0E,
+INIT_0F => PM_Inst_RAM_Word4_INIT_0F,
+INIT_10 => PM_Inst_RAM_Word4_INIT_10,
+INIT_11 => PM_Inst_RAM_Word4_INIT_11,
+INIT_12 => PM_Inst_RAM_Word4_INIT_12,
+INIT_13 => PM_Inst_RAM_Word4_INIT_13,
+INIT_14 => PM_Inst_RAM_Word4_INIT_14,
+INIT_15 => PM_Inst_RAM_Word4_INIT_15,
+INIT_16 => PM_Inst_RAM_Word4_INIT_16,
+INIT_17 => PM_Inst_RAM_Word4_INIT_17,
+INIT_18 => PM_Inst_RAM_Word4_INIT_18,
+INIT_19 => PM_Inst_RAM_Word4_INIT_19,
+INIT_1A => PM_Inst_RAM_Word4_INIT_1A,
+INIT_1B => PM_Inst_RAM_Word4_INIT_1B,
+INIT_1C => PM_Inst_RAM_Word4_INIT_1C,
+INIT_1D => PM_Inst_RAM_Word4_INIT_1D,
+INIT_1E => PM_Inst_RAM_Word4_INIT_1E,
+INIT_1F => PM_Inst_RAM_Word4_INIT_1F,
+INIT_20 => PM_Inst_RAM_Word4_INIT_20,
+INIT_21 => PM_Inst_RAM_Word4_INIT_21,
+INIT_22 => PM_Inst_RAM_Word4_INIT_22,
+INIT_23 => PM_Inst_RAM_Word4_INIT_23,
+INIT_24 => PM_Inst_RAM_Word4_INIT_24,
+INIT_25 => PM_Inst_RAM_Word4_INIT_25,
+INIT_26 => PM_Inst_RAM_Word4_INIT_26,
+INIT_27 => PM_Inst_RAM_Word4_INIT_27,
+INIT_28 => PM_Inst_RAM_Word4_INIT_28,
+INIT_29 => PM_Inst_RAM_Word4_INIT_29,
+INIT_2A => PM_Inst_RAM_Word4_INIT_2A,
+INIT_2B => PM_Inst_RAM_Word4_INIT_2B,
+INIT_2C => PM_Inst_RAM_Word4_INIT_2C,
+INIT_2D => PM_Inst_RAM_Word4_INIT_2D,
+INIT_2E => PM_Inst_RAM_Word4_INIT_2E,
+INIT_2F => PM_Inst_RAM_Word4_INIT_2F,
+-- Address 768 to 1023
+INIT_30 => PM_Inst_RAM_Word4_INIT_30,
+INIT_31 => PM_Inst_RAM_Word4_INIT_31,
+INIT_32 => PM_Inst_RAM_Word4_INIT_32,
+INIT_33 => PM_Inst_RAM_Word4_INIT_33,
+INIT_34 => PM_Inst_RAM_Word4_INIT_34,
+INIT_35 => PM_Inst_RAM_Word4_INIT_35,
+INIT_36 => PM_Inst_RAM_Word4_INIT_36,
+INIT_37 => PM_Inst_RAM_Word4_INIT_37,
+INIT_38 => PM_Inst_RAM_Word4_INIT_38,
+INIT_39 => PM_Inst_RAM_Word4_INIT_39,
+INIT_3A => PM_Inst_RAM_Word4_INIT_3A,
+INIT_3B => PM_Inst_RAM_Word4_INIT_3B,
+INIT_3C => PM_Inst_RAM_Word4_INIT_3C,
+INIT_3D => PM_Inst_RAM_Word4_INIT_3D,
+INIT_3E => PM_Inst_RAM_Word4_INIT_3E,
+INIT_3F => PM_Inst_RAM_Word4_INIT_3F
+)
+port map(
+                                      DO   => RAMBlDOut(4)(15 downto 0),
+                                      ADDR => address(9 downto 0),
+                                      DI   => din(15 downto 0),
+												  DIP  => DIP,
+                                      EN   => ce,
+												  SSR  => SSR,
+                                      CLK  => cp2,
+                                      WE   => WEB(4)
+                                      );
+
+RAM_Word5:component RAMB16_S18 
+generic map (
+INIT => X"00000", -- Value of output RAM registers at startup
+SRVAL => X"00000", -- Ouput value upon SSR assertion
+WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+-- The following INIT_xx declarations specify the intial contents of the RAM
+-- Address 0 to 255
+INIT_00 => PM_Inst_RAM_Word5_INIT_00,
+INIT_01 => PM_Inst_RAM_Word5_INIT_01,
+INIT_02 => PM_Inst_RAM_Word5_INIT_02,
+INIT_03 => PM_Inst_RAM_Word5_INIT_03,
+INIT_04 => PM_Inst_RAM_Word5_INIT_04,
+INIT_05 => PM_Inst_RAM_Word5_INIT_05,
+INIT_06 => PM_Inst_RAM_Word5_INIT_06,
+INIT_07 => PM_Inst_RAM_Word5_INIT_07,
+INIT_08 => PM_Inst_RAM_Word5_INIT_08,
+INIT_09 => PM_Inst_RAM_Word5_INIT_09,
+INIT_0A => PM_Inst_RAM_Word5_INIT_0A,
+INIT_0B => PM_Inst_RAM_Word5_INIT_0B,
+INIT_0C => PM_Inst_RAM_Word5_INIT_0C,
+INIT_0D => PM_Inst_RAM_Word5_INIT_0D,
+INIT_0E => PM_Inst_RAM_Word5_INIT_0E,
+INIT_0F => PM_Inst_RAM_Word5_INIT_0F,
+INIT_10 => PM_Inst_RAM_Word5_INIT_10,
+INIT_11 => PM_Inst_RAM_Word5_INIT_11,
+INIT_12 => PM_Inst_RAM_Word5_INIT_12,
+INIT_13 => PM_Inst_RAM_Word5_INIT_13,
+INIT_14 => PM_Inst_RAM_Word5_INIT_14,
+INIT_15 => PM_Inst_RAM_Word5_INIT_15,
+INIT_16 => PM_Inst_RAM_Word5_INIT_16,
+INIT_17 => PM_Inst_RAM_Word5_INIT_17,
+INIT_18 => PM_Inst_RAM_Word5_INIT_18,
+INIT_19 => PM_Inst_RAM_Word5_INIT_19,
+INIT_1A => PM_Inst_RAM_Word5_INIT_1A,
+INIT_1B => PM_Inst_RAM_Word5_INIT_1B,
+INIT_1C => PM_Inst_RAM_Word5_INIT_1C,
+INIT_1D => PM_Inst_RAM_Word5_INIT_1D,
+INIT_1E => PM_Inst_RAM_Word5_INIT_1E,
+INIT_1F => PM_Inst_RAM_Word5_INIT_1F,
+INIT_20 => PM_Inst_RAM_Word5_INIT_20,
+INIT_21 => PM_Inst_RAM_Word5_INIT_21,
+INIT_22 => PM_Inst_RAM_Word5_INIT_22,
+INIT_23 => PM_Inst_RAM_Word5_INIT_23,
+INIT_24 => PM_Inst_RAM_Word5_INIT_24,
+INIT_25 => PM_Inst_RAM_Word5_INIT_25,
+INIT_26 => PM_Inst_RAM_Word5_INIT_26,
+INIT_27 => PM_Inst_RAM_Word5_INIT_27,
+INIT_28 => PM_Inst_RAM_Word5_INIT_28,
+INIT_29 => PM_Inst_RAM_Word5_INIT_29,
+INIT_2A => PM_Inst_RAM_Word5_INIT_2A,
+INIT_2B => PM_Inst_RAM_Word5_INIT_2B,
+INIT_2C => PM_Inst_RAM_Word5_INIT_2C,
+INIT_2D => PM_Inst_RAM_Word5_INIT_2D,
+INIT_2E => PM_Inst_RAM_Word5_INIT_2E,
+INIT_2F => PM_Inst_RAM_Word5_INIT_2F,
+-- Address 768 to 1023
+INIT_30 => PM_Inst_RAM_Word5_INIT_30,
+INIT_31 => PM_Inst_RAM_Word5_INIT_31,
+INIT_32 => PM_Inst_RAM_Word5_INIT_32,
+INIT_33 => PM_Inst_RAM_Word5_INIT_33,
+INIT_34 => PM_Inst_RAM_Word5_INIT_34,
+INIT_35 => PM_Inst_RAM_Word5_INIT_35,
+INIT_36 => PM_Inst_RAM_Word5_INIT_36,
+INIT_37 => PM_Inst_RAM_Word5_INIT_37,
+INIT_38 => PM_Inst_RAM_Word5_INIT_38,
+INIT_39 => PM_Inst_RAM_Word5_INIT_39,
+INIT_3A => PM_Inst_RAM_Word5_INIT_3A,
+INIT_3B => PM_Inst_RAM_Word5_INIT_3B,
+INIT_3C => PM_Inst_RAM_Word5_INIT_3C,
+INIT_3D => PM_Inst_RAM_Word5_INIT_3D,
+INIT_3E => PM_Inst_RAM_Word5_INIT_3E,
+INIT_3F => PM_Inst_RAM_Word5_INIT_3F
+)
+port map(
+                                      DO   => RAMBlDOut(5)(15 downto 0),
+                                      ADDR => address(9 downto 0),
+                                      DI   => din(15 downto 0),
+												  DIP  => DIP,
+                                      EN   => ce,
+												  SSR  => SSR,
+                                      CLK  => cp2,
+                                      WE   => WEB(5)
+                                      );
+
+RAM_Word6:component RAMB16_S18 
+generic map (
+INIT => X"00000", -- Value of output RAM registers at startup
+SRVAL => X"00000", -- Ouput value upon SSR assertion
+WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+-- The following INIT_xx declarations specify the intial contents of the RAM
+-- Address 0 to 255
+INIT_00 => PM_Inst_RAM_Word6_INIT_00,
+INIT_01 => PM_Inst_RAM_Word6_INIT_01,
+INIT_02 => PM_Inst_RAM_Word6_INIT_02,
+INIT_03 => PM_Inst_RAM_Word6_INIT_03,
+INIT_04 => PM_Inst_RAM_Word6_INIT_04,
+INIT_05 => PM_Inst_RAM_Word6_INIT_05,
+INIT_06 => PM_Inst_RAM_Word6_INIT_06,
+INIT_07 => PM_Inst_RAM_Word6_INIT_07,
+INIT_08 => PM_Inst_RAM_Word6_INIT_08,
+INIT_09 => PM_Inst_RAM_Word6_INIT_09,
+INIT_0A => PM_Inst_RAM_Word6_INIT_0A,
+INIT_0B => PM_Inst_RAM_Word6_INIT_0B,
+INIT_0C => PM_Inst_RAM_Word6_INIT_0C,
+INIT_0D => PM_Inst_RAM_Word6_INIT_0D,
+INIT_0E => PM_Inst_RAM_Word6_INIT_0E,
+INIT_0F => PM_Inst_RAM_Word6_INIT_0F,
+INIT_10 => PM_Inst_RAM_Word6_INIT_10,
+INIT_11 => PM_Inst_RAM_Word6_INIT_11,
+INIT_12 => PM_Inst_RAM_Word6_INIT_12,
+INIT_13 => PM_Inst_RAM_Word6_INIT_13,
+INIT_14 => PM_Inst_RAM_Word6_INIT_14,
+INIT_15 => PM_Inst_RAM_Word6_INIT_15,
+INIT_16 => PM_Inst_RAM_Word6_INIT_16,
+INIT_17 => PM_Inst_RAM_Word6_INIT_17,
+INIT_18 => PM_Inst_RAM_Word6_INIT_18,
+INIT_19 => PM_Inst_RAM_Word6_INIT_19,
+INIT_1A => PM_Inst_RAM_Word6_INIT_1A,
+INIT_1B => PM_Inst_RAM_Word6_INIT_1B,
+INIT_1C => PM_Inst_RAM_Word6_INIT_1C,
+INIT_1D => PM_Inst_RAM_Word6_INIT_1D,
+INIT_1E => PM_Inst_RAM_Word6_INIT_1E,
+INIT_1F => PM_Inst_RAM_Word6_INIT_1F,
+INIT_20 => PM_Inst_RAM_Word6_INIT_20,
+INIT_21 => PM_Inst_RAM_Word6_INIT_21,
+INIT_22 => PM_Inst_RAM_Word6_INIT_22,
+INIT_23 => PM_Inst_RAM_Word6_INIT_23,
+INIT_24 => PM_Inst_RAM_Word6_INIT_24,
+INIT_25 => PM_Inst_RAM_Word6_INIT_25,
+INIT_26 => PM_Inst_RAM_Word6_INIT_26,
+INIT_27 => PM_Inst_RAM_Word6_INIT_27,
+INIT_28 => PM_Inst_RAM_Word6_INIT_28,
+INIT_29 => PM_Inst_RAM_Word6_INIT_29,
+INIT_2A => PM_Inst_RAM_Word6_INIT_2A,
+INIT_2B => PM_Inst_RAM_Word6_INIT_2B,
+INIT_2C => PM_Inst_RAM_Word6_INIT_2C,
+INIT_2D => PM_Inst_RAM_Word6_INIT_2D,
+INIT_2E => PM_Inst_RAM_Word6_INIT_2E,
+INIT_2F => PM_Inst_RAM_Word6_INIT_2F,
+-- Address 768 to 1023
+INIT_30 => PM_Inst_RAM_Word6_INIT_30,
+INIT_31 => PM_Inst_RAM_Word6_INIT_31,
+INIT_32 => PM_Inst_RAM_Word6_INIT_32,
+INIT_33 => PM_Inst_RAM_Word6_INIT_33,
+INIT_34 => PM_Inst_RAM_Word6_INIT_34,
+INIT_35 => PM_Inst_RAM_Word6_INIT_35,
+INIT_36 => PM_Inst_RAM_Word6_INIT_36,
+INIT_37 => PM_Inst_RAM_Word6_INIT_37,
+INIT_38 => PM_Inst_RAM_Word6_INIT_38,
+INIT_39 => PM_Inst_RAM_Word6_INIT_39,
+INIT_3A => PM_Inst_RAM_Word6_INIT_3A,
+INIT_3B => PM_Inst_RAM_Word6_INIT_3B,
+INIT_3C => PM_Inst_RAM_Word6_INIT_3C,
+INIT_3D => PM_Inst_RAM_Word6_INIT_3D,
+INIT_3E => PM_Inst_RAM_Word6_INIT_3E,
+INIT_3F => PM_Inst_RAM_Word6_INIT_3F
+)
+port map(
+                                      DO   => RAMBlDOut(6)(15 downto 0),
+                                      ADDR => address(9 downto 0),
+                                      DI   => din(15 downto 0),
+												  DIP  => DIP,
+                                      EN   => ce,
+												  SSR  => SSR,
+                                      CLK  => cp2,
+                                      WE   => WEB(6)
+                                      );
+
+RAM_Word7:component RAMB16_S18 
+generic map (
+INIT => X"00000", -- Value of output RAM registers at startup
+SRVAL => X"00000", -- Ouput value upon SSR assertion
+WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+-- The following INIT_xx declarations specify the intial contents of the RAM
+-- Address 0 to 255
+INIT_00 => PM_Inst_RAM_Word7_INIT_00,
+INIT_01 => PM_Inst_RAM_Word7_INIT_01,
+INIT_02 => PM_Inst_RAM_Word7_INIT_02,
+INIT_03 => PM_Inst_RAM_Word7_INIT_03,
+INIT_04 => PM_Inst_RAM_Word7_INIT_04,
+INIT_05 => PM_Inst_RAM_Word7_INIT_05,
+INIT_06 => PM_Inst_RAM_Word7_INIT_06,
+INIT_07 => PM_Inst_RAM_Word7_INIT_07,
+INIT_08 => PM_Inst_RAM_Word7_INIT_08,
+INIT_09 => PM_Inst_RAM_Word7_INIT_09,
+INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
+INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
+INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
+INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
+INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
+INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
+INIT_10 => PM_Inst_RAM_Word7_INIT_10,
+INIT_11 => PM_Inst_RAM_Word7_INIT_11,
+INIT_12 => PM_Inst_RAM_Word7_INIT_12,
+INIT_13 => PM_Inst_RAM_Word7_INIT_13,
+INIT_14 => PM_Inst_RAM_Word7_INIT_14,
+INIT_15 => PM_Inst_RAM_Word7_INIT_15,
+INIT_16 => PM_Inst_RAM_Word7_INIT_16,
+INIT_17 => PM_Inst_RAM_Word7_INIT_17,
+INIT_18 => PM_Inst_RAM_Word7_INIT_18,
+INIT_19 => PM_Inst_RAM_Word7_INIT_19,
+INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
+INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
+INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
+INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
+INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
+INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
+INIT_20 => PM_Inst_RAM_Word7_INIT_20,
+INIT_21 => PM_Inst_RAM_Word7_INIT_21,
+INIT_22 => PM_Inst_RAM_Word7_INIT_22,
+INIT_23 => PM_Inst_RAM_Word7_INIT_23,
+INIT_24 => PM_Inst_RAM_Word7_INIT_24,
+INIT_25 => PM_Inst_RAM_Word7_INIT_25,
+INIT_26 => PM_Inst_RAM_Word7_INIT_26,
+INIT_27 => PM_Inst_RAM_Word7_INIT_27,
+INIT_28 => PM_Inst_RAM_Word7_INIT_28,
+INIT_29 => PM_Inst_RAM_Word7_INIT_29,
+INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
+INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
+INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
+INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
+INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
+INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
+-- Address 768 to 1023
+INIT_30 => PM_Inst_RAM_Word7_INIT_30,
+INIT_31 => PM_Inst_RAM_Word7_INIT_31,
+INIT_32 => PM_Inst_RAM_Word7_INIT_32,
+INIT_33 => PM_Inst_RAM_Word7_INIT_33,
+INIT_34 => PM_Inst_RAM_Word7_INIT_34,
+INIT_35 => PM_Inst_RAM_Word7_INIT_35,
+INIT_36 => PM_Inst_RAM_Word7_INIT_36,
+INIT_37 => PM_Inst_RAM_Word7_INIT_37,
+INIT_38 => PM_Inst_RAM_Word7_INIT_38,
+INIT_39 => PM_Inst_RAM_Word7_INIT_39,
+INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
+INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
+INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
+INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
+INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
+INIT_3F => PM_Inst_RAM_Word7_INIT_3F
+)
+port map(
+                                      DO   => RAMBlDOut(7)(15 downto 0),
+                                      ADDR => address(9 downto 0),
+                                      DI   => din(15 downto 0),
+												  DIP  => DIP,
+                                      EN   => ce,
+												  SSR  => SSR,
+                                      CLK  => cp2,
+                                      WE   => WEB(7)
+                                      );												  
+									  
+--end generate;
+
+RAM_Word8:component RAMB16_S18 
+generic map (
+INIT => X"00000", -- Value of output RAM registers at startup
+SRVAL => X"00000", -- Ouput value upon SSR assertion
+WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+-- The following INIT_xx declarations specify the intial contents of the RAM
+-- Address 0 to 255
+INIT_00 => PM_Inst_RAM_Word7_INIT_00,
+INIT_01 => PM_Inst_RAM_Word7_INIT_01,
+INIT_02 => PM_Inst_RAM_Word7_INIT_02,
+INIT_03 => PM_Inst_RAM_Word7_INIT_03,
+INIT_04 => PM_Inst_RAM_Word7_INIT_04,
+INIT_05 => PM_Inst_RAM_Word7_INIT_05,
+INIT_06 => PM_Inst_RAM_Word7_INIT_06,
+INIT_07 => PM_Inst_RAM_Word7_INIT_07,
+INIT_08 => PM_Inst_RAM_Word7_INIT_08,
+INIT_09 => PM_Inst_RAM_Word7_INIT_09,
+INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
+INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
+INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
+INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
+INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
+INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
+INIT_10 => PM_Inst_RAM_Word7_INIT_10,
+INIT_11 => PM_Inst_RAM_Word7_INIT_11,
+INIT_12 => PM_Inst_RAM_Word7_INIT_12,
+INIT_13 => PM_Inst_RAM_Word7_INIT_13,
+INIT_14 => PM_Inst_RAM_Word7_INIT_14,
+INIT_15 => PM_Inst_RAM_Word7_INIT_15,
+INIT_16 => PM_Inst_RAM_Word7_INIT_16,
+INIT_17 => PM_Inst_RAM_Word7_INIT_17,
+INIT_18 => PM_Inst_RAM_Word7_INIT_18,
+INIT_19 => PM_Inst_RAM_Word7_INIT_19,
+INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
+INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
+INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
+INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
+INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
+INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
+INIT_20 => PM_Inst_RAM_Word7_INIT_20,
+INIT_21 => PM_Inst_RAM_Word7_INIT_21,
+INIT_22 => PM_Inst_RAM_Word7_INIT_22,
+INIT_23 => PM_Inst_RAM_Word7_INIT_23,
+INIT_24 => PM_Inst_RAM_Word7_INIT_24,
+INIT_25 => PM_Inst_RAM_Word7_INIT_25,
+INIT_26 => PM_Inst_RAM_Word7_INIT_26,
+INIT_27 => PM_Inst_RAM_Word7_INIT_27,
+INIT_28 => PM_Inst_RAM_Word7_INIT_28,
+INIT_29 => PM_Inst_RAM_Word7_INIT_29,
+INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
+INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
+INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
+INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
+INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
+INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
+-- Address 768 to 1023
+INIT_30 => PM_Inst_RAM_Word7_INIT_30,
+INIT_31 => PM_Inst_RAM_Word7_INIT_31,
+INIT_32 => PM_Inst_RAM_Word7_INIT_32,
+INIT_33 => PM_Inst_RAM_Word7_INIT_33,
+INIT_34 => PM_Inst_RAM_Word7_INIT_34,
+INIT_35 => PM_Inst_RAM_Word7_INIT_35,
+INIT_36 => PM_Inst_RAM_Word7_INIT_36,
+INIT_37 => PM_Inst_RAM_Word7_INIT_37,
+INIT_38 => PM_Inst_RAM_Word7_INIT_38,
+INIT_39 => PM_Inst_RAM_Word7_INIT_39,
+INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
+INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
+INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
+INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
+INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
+INIT_3F => PM_Inst_RAM_Word7_INIT_3F
+)
+port map(
+                                      DO   => RAMBlDOut(8)(15 downto 0),
+                                      ADDR => address(9 downto 0),
+                                      DI   => din(15 downto 0),
+												  DIP  => DIP,
+                                      EN   => ce,
+												  SSR  => SSR,
+                                      CLK  => cp2,
+                                      WE   => WEB(8)
+                                      );												  
+									  
+--end generate;
+
+
+
+
+
+        
+-- Output data mux
+dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 10)));
+
+
+
+end RTL;

src/AVR8/uC/AVR8.vhd

@@ -78,7 +78,7 @@ constant CImplSPI            				: boolean := FALSE;   -- adding SPI master
 constant CImplTmrCnt     					: boolean := FALSE;	--AVR8 Timer
 constant CImplExtIRQ				: boolean := FALSE;	--AVR8 Interrupt Unit
 
-component XDM4Kx8	port(
+component XDM2Kx8	port(
 	                cp2       : in  std_logic;
 						 ce        : in  std_logic;
 	                address   : in  std_logic_vector(CDATAMEMSIZE downto 0); 
@@ -88,7 +88,7 @@ component XDM4Kx8	port(
 					   );
 end component;
 
-component XPM8Kx16 port(
+component XPM9Kx16 port(
 	                  cp2     : in  std_logic;
 					  ce      : in  std_logic;
 	                  address : in  std_logic_vector(CPROGMEMSIZE downto 0); 
@@ -773,7 +773,7 @@ end generate;
 ram_cp2_n <= not clk16M;
 
 ---- Data memory(8-bit)					   
-DRAM_Inst:component XDM4Kx8 
+DRAM_Inst:component XDM2Kx8 
 port map(
 	                    cp2       => ram_cp2_n,
 						ce        => vcc,
@@ -784,7 +784,7 @@ port map(
 					   );
 
 -- Program memory					   
-PM_Inst:component XPM8Kx16 
+PM_Inst:component XPM9Kx16 
 port map(
 	                  cp2     => ram_cp2_n, 
 					  ce      => vcc,

src/AtomCpuMon.bmm

@@ -1,6 +1,6 @@
 ADDRESS_MAP avrmap PPC405 0
 
-    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
+    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
         BUS_BLOCK
 	    mon/Inst_AVR8/PM_Inst/RAM_Word0 [15:0];
         END_BUS_BLOCK;
@@ -33,6 +33,10 @@ ADDRESS_MAP avrmap PPC405 0
 	    mon/Inst_AVR8/PM_Inst/RAM_Word7 [15:0];
         END_BUS_BLOCK;	
 		  
+        BUS_BLOCK
+	    mon/Inst_AVR8/PM_Inst/RAM_Word8 [15:0];
+        END_BUS_BLOCK;	
+		  
     END_ADDRESS_SPACE;
 
 END_ADDRESS_MAP;

src/MC6809ECpuMon.bmm

@@ -1,6 +1,6 @@
 ADDRESS_MAP avrmap PPC405 0
 
-    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
+    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
         BUS_BLOCK
 	    mon/Inst_AVR8/PM_Inst/RAM_Word0 [15:0];
         END_BUS_BLOCK;
@@ -33,6 +33,10 @@ ADDRESS_MAP avrmap PPC405 0
 	    mon/Inst_AVR8/PM_Inst/RAM_Word7 [15:0];
         END_BUS_BLOCK;	
 		  
+        BUS_BLOCK
+	    mon/Inst_AVR8/PM_Inst/RAM_Word8 [15:0];
+        END_BUS_BLOCK;	
+
     END_ADDRESS_SPACE;
 
 END_ADDRESS_MAP;

src/Z80CpuMon.bmm

@@ -1,6 +1,6 @@
 ADDRESS_MAP avrmap PPC405 0
 
-    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
+    ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
         BUS_BLOCK
 	    mon/Inst_AVR8/PM_Inst/RAM_Word0 [15:0];
         END_BUS_BLOCK;
@@ -33,6 +33,10 @@ ADDRESS_MAP avrmap PPC405 0
 	    mon/Inst_AVR8/PM_Inst/RAM_Word7 [15:0];
         END_BUS_BLOCK;	
 		  
+        BUS_BLOCK
+	    mon/Inst_AVR8/PM_Inst/RAM_Word8 [15:0];
+        END_BUS_BLOCK;	
+		  
     END_ADDRESS_SPACE;
 
 END_ADDRESS_MAP;