diff --git a/src/AtomBusMon.vhd b/src/AtomBusMon.vhd
index 8d5fada..677b756 100644
--- a/src/AtomBusMon.vhd
+++ b/src/AtomBusMon.vhd
@@ -76,6 +76,7 @@ begin
         Rdy     => Rdy,
         nRSTin  => nRST,
         nRSTout => nRST,
+        CountCycle => Rdy,
         Regs    => (others => '0'),
         RdOut   => open,
         WrOut   => open,
diff --git a/src/AtomCpuMon.vhd b/src/AtomCpuMon.vhd
index b52be28..04665a8 100644
--- a/src/AtomCpuMon.vhd
+++ b/src/AtomCpuMon.vhd
@@ -111,6 +111,7 @@ begin
         Rdy     => Rdy_int,
         nRSTin  => Res_n,
         nRSTout => Res_n,
+        CountCycle => Rdy_int,
         trig    => trig,
         lcd_rs  => open,
         lcd_rw  => open,
diff --git a/src/BusMonCore.vhd b/src/BusMonCore.vhd
index 96488a9..3f75dc7 100644
--- a/src/BusMonCore.vhd
+++ b/src/BusMonCore.vhd
@@ -41,6 +41,8 @@ entity BusMonCore is
         Rdy              : out   std_logic;
         nRSTin           : in    std_logic;
         nRSTout          : out   std_logic;
+
+        CountCycle       : in    std_logic;
         
         -- 6502 Registers
         -- unused in pure bus monitor mode
@@ -418,7 +420,7 @@ begin
             -- Cycle counter, wraps every 16s at 1MHz
             if (nRSTin = '0') then
                 cycleCount <= (others => '0');
-            elsif (Rdy_int = '1') then
+            elsif (CountCycle = '1') then
                 cycleCount <= cycleCount + 1;
             end if;
         
diff --git a/src/Z80CpuMon.vhd b/src/Z80CpuMon.vhd
index c3f247a..581fe7a 100644
--- a/src/Z80CpuMon.vhd
+++ b/src/Z80CpuMon.vhd
@@ -97,6 +97,7 @@ signal TState : std_logic_vector(2 downto 0);
 signal SS_Single : std_logic;
 signal SS_Step : std_logic;
 signal SS_Step_held : std_logic;
+signal CountCycle : std_logic;
 
 signal Regs : std_logic_vector(255 downto 0);        
 signal memory_rd     : std_logic;
@@ -145,6 +146,7 @@ begin
         Rdy     => Rdy,
         nRSTin  => RESET_n_int,
         nRSTout => nRST,
+        CountCycle => CountCycle,
         trig    => trig,
         lcd_rs  => open,
         lcd_rw  => open,
@@ -198,6 +200,8 @@ begin
  
     WAIT_n_int <= WAIT_n when SS_Single = '0' else
                   WAIT_n and SS_Step_held;
+                  
+    CountCycle <= '1' when SS_Single = '0' or SS_Step_held = '1' else '0';
 
     sync_gen : process(CLK_n, RESET_n_int)
     begin