ICE T65: Fixed the single stepping issue with AlanD's core (sync bug); increased CCLK rate to 25MHz

Change-Id: I226a63a10b80973001f4b0ee825dcecadaece8cb

src/AlanD/R65Cx2.vhd

@@ -1187,7 +1187,7 @@ calcT: process(clk)
 -- -----------------------------------------------------------------------
 -- I flag interupt flag
 -- -----------------------------------------------------------------------
-	process(clk)
+	process(clk, reset)
 	begin
 	if reset = '0' then
       I <= '1';
@@ -1202,7 +1202,7 @@ calcT: process(clk)
 -- -----------------------------------------------------------------------
 -- D flag
 -- -----------------------------------------------------------------------
-	process(clk)
+	process(clk, reset)
 	begin
 	if reset = '0' then
       D <= '0';
@@ -1502,18 +1502,22 @@ calcAddr: process(clk)
 	myAddrDecrH <= myAddr(15 downto 8) - 1;
 	addr <= myAddr;
 	
-	calcsync: process(clk)
-	begin
-		
-			if enable = '1' then
-				case theCpuCycle is
-				when opcodeFetch =>			sync <= '1';
-				when others =>					sync <= '0';			
-				end case;
-			end if;
-	end process;
+-- DMB This looked plain broken and inferred a latch
+--    
+--	calcsync: process(clk)
+--	begin
+--		
+--			if enable = '1' then
+--				case theCpuCycle is
+--				when opcodeFetch =>			sync <= '1';
+--				when others =>					sync <= '0';			
+--				end case;
+--			end if;
+--	end process;
+
+   sync <= '1' when theCpuCycle = opcodeFetch else '0';
 	
-		sync_irq <= irqActive;
+   sync_irq <= irqActive;
 
    Regs <= std_logic_vector(PC) &
            "00000001" & std_logic_vector(S)& 

src/AtomCpuMon.vhd

@@ -198,9 +198,6 @@ begin
         );
     end generate;    
     
-    -- IMPORTANT NOTE:
-    -- Single Stepping does not seem to be currently working with AlanD's 65C02 core
-    -- Commit 344e0318 likely broke it 
     GenAlanDCore: if UseAlanDCore generate
         inst_r65c02: entity work.r65c02 port map (
             reset    => RES_n,