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AtomBusMon
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Added build scripts for xc3s500e 

Change-Id: Icc7990c3ee257d1511fa478fd0d2b3575362eb29
This commit is contained in:
David Banks 2016-10-24 14:24:18 +01:00
parent 0692e204e8
commit f64641f99c
41 changed files with 18070 additions and 52 deletions
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18
.gitignore vendored
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@ -4,14 +4,20 @@ working/
nohup.out
AtomBusMon_guide.ncd
AtomBusMon_summary.html
src/AtomBusMon_bd.bmm
src/AtomCpuMon_bd.bmm
src/AtomCpuMon_bd.bmm
src/AtomFast6502_bd.bmm
src/Z80CpuMon_bd.bmm
src/MC6809ECpuMon_bd.bmm
src/250/AtomBusMon_bd.bmm
src/250/AtomCpuMon_bd.bmm
src/250/AtomFast6502_bd.bmm
src/250/Z80CpuMon_bd.bmm
src/250/MC6809ECpuMon_bd.bmm
src/500/AtomBusMon_bd.bmm
src/500/AtomCpuMon_bd.bmm
src/500/AtomFast6502_bd.bmm
src/500/Z80CpuMon_bd.bmm
src/500/MC6809ECpuMon_bd.bmm
*~
#*
build_250.log
build_500.log
firmware/*.o
firmware/*.bit
firmware/avr_progmem.*

6
AtomBusMon.xise
View File

@ -203,7 +203,7 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="src/AtomBusMon.bmm" xil_pn:type="FILE_BMM">
<file xil_pn:name="src/250/AtomBusMon.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="src/oho_dy1/Oho_Dy1.vhd" xil_pn:type="FILE_VHDL">
@ -334,7 +334,7 @@
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AtomBusMon|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../src/AtomBusMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../src/AtomBusMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AtomBusMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -511,7 +511,7 @@
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working/250" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->

6
AtomCpuMon.xise
View File

@ -254,7 +254,7 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="src/AtomCpuMon.bmm" xil_pn:type="FILE_BMM">
<file xil_pn:name="src/250/AtomCpuMon.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
@ -367,7 +367,7 @@
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AtomCpuMon|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../src/AtomCpuMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../src/AtomCpuMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -544,7 +544,7 @@
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working/250" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->

6
AtomFast6502.xise
View File

@ -234,7 +234,7 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="src/AtomFast6502.bmm" xil_pn:type="FILE_BMM">
<file xil_pn:name="src/250/AtomFast6502.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="src/BusMonCore.vhd" xil_pn:type="FILE_VHDL">
@ -370,7 +370,7 @@
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AtomFast6502|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../src/AtomFast6502.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../src/AtomFast6502.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AtomFast6502" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -547,7 +547,7 @@
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working/250" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->

2
Blank.xise
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@ -347,7 +347,7 @@
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working/250" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->

13
MC6809ECpuMon.xise
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@ -222,7 +222,7 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="src/MC6809ECpuMon.bmm" xil_pn:type="FILE_BMM">
<file xil_pn:name="src/250/MC6809ECpuMon.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="src/DCM/DCM1.vhd" xil_pn:type="FILE_VHDL">
@ -252,7 +252,7 @@
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -347,7 +347,7 @@
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809ECpuMon|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../src/MC6809ECpuMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../src/MC6809ECpuMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809ECpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -524,7 +524,7 @@
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working/250" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
@ -545,10 +545,7 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/MC6809ECpuMon" xil_pn:name="src/MC6809ECpuMon.ucf"/>
<binding xil_pn:location="/MC6809EECpuMon" xil_pn:name="src/MC6809ECpuMon.bmm"/>
</bindings>
<bindings/>
<libraries/>

8
Z80CpuMon.xise
View File

@ -254,7 +254,7 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="src/Z80CpuMon.bmm" xil_pn:type="FILE_BMM">
<file xil_pn:name="src/250/Z80CpuMon.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
@ -286,7 +286,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@ -366,7 +366,7 @@
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Z80CpuMon|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../src/Z80CpuMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../src/Z80CpuMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Z80CpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -543,7 +543,7 @@
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working/250" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->

12
build_250.sh Executable file
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@ -0,0 +1,12 @@
#!/bin/bash
# Reset the logfile
rm -f build_250.log
# Compile the Xilinx Designs
./ise_clean.tcl 2>&1 | tee -a build_250.log
./ise_build.tcl 2>&1 | tee -a build_250.log
# Build the firmware release
./gen_mcs.sh 250 2>&1 | tee -a build_250.log

30
build_500.sh Executable file
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@ -0,0 +1,30 @@
#!/bin/bash
# Create custom versions of all the scripts and projects
sed "s/.xise/_500.xise/" < ise_clean.tcl > ise_clean_500.tcl
sed "s/.xise/_500.xise/" < ise_build.tcl > ise_build_500.tcl
chmod +x ./ise_clean_500.tcl
chmod +x ./ise_build_500.tcl
PROJECTS=`/bin/ls [A-Za-z0-9]*.xise`
for i in $PROJECTS
do
cat $i | sed "s/xc3s250e/xc3s500e/" | sed "s#working/250#working/500#" | sed "s#src/250#src/500#" > `basename $i .xise`_500.xise
done
# Reset the logfile
rm -f build_500.log
# Compile the Xilinx Designs
./ise_clean_500.tcl 2>&1 | tee -a build_500.log
./ise_build_500.tcl 2>&1 | tee -a build_500.log
# Build the firmware release
./gen_mcs.sh 500 2>&1 | tee -a build_500.log
# Clean up
rm -f *_500.tcl
rm -f *_500.xise

10
firmware/Makefile.6502cpu
View File

@ -1,18 +1,20 @@
# Paths that will need changing
# default to the xc3s250e part
WORKING_DIR=working/250
SRC_DIR=src/250
ATOMFPGA=$(HOME)/atom/AtomBusMon
PAPILIO_LOADER=/opt/GadgetFactory/papilio-loader/programmer
XILINX=/opt/Xilinx/14.7
# Shouldn't need to make changes below this point
BIT_FILE=$(ATOMFPGA)/working/AtomCpuMon.bit
BMM_FILE=$(ATOMFPGA)/src/AtomCpuMon_bd.bmm
BIT_FILE=$(ATOMFPGA)/$(WORKING_DIR)/AtomCpuMon.bit
BMM_FILE=$(ATOMFPGA)/$(SRC_DIR)/AtomCpuMon_bd.bmm
# Papilio dev environment
PROG=${PAPILIO_LOADER}/linux32/papilio-prog
BSCAN=${PAPILIO_LOADER}/bscan_spi_xc3s500e.bit
SREC_CAT=srec_cat
GAWK=gawk
DATA2MEM=${XILINX}/ISE_DS/ISE/bin/lin/data2mem

10
firmware/Makefile.6502fast
View File

@ -1,18 +1,20 @@
# Paths that will need changing
# default to the xc3s250e part
WORKING_DIR=working/250
SRC_DIR=src/250
ATOMFPGA=$(HOME)/atom/AtomBusMon
PAPILIO_LOADER=/opt/GadgetFactory/papilio-loader/programmer
XILINX=/opt/Xilinx/14.7
# Shouldn't need to make changes below this point
BIT_FILE=$(ATOMFPGA)/working/AtomFast6502.bit
BMM_FILE=$(ATOMFPGA)/src/AtomFast6502_bd.bmm
BIT_FILE=$(ATOMFPGA)/$(WORKING_DIR)/AtomFast6502.bit
BMM_FILE=$(ATOMFPGA)/$(SRC_DIR)/AtomFast6502_bd.bmm
# Papilio dev environment
PROG=${PAPILIO_LOADER}/linux32/papilio-prog
BSCAN=${PAPILIO_LOADER}/bscan_spi_xc3s500e.bit
SREC_CAT=srec_cat
GAWK=gawk
DATA2MEM=${XILINX}/ISE_DS/ISE/bin/lin/data2mem

10
firmware/Makefile.6502mon
View File

@ -1,18 +1,20 @@
# Paths that will need changing
# default to the xc3s250e part
WORKING_DIR=working/250
SRC_DIR=src/250
ATOMFPGA=$(HOME)/atom/AtomBusMon
PAPILIO_LOADER=/opt/GadgetFactory/papilio-loader/programmer
XILINX=/opt/Xilinx/14.7
# Shouldn't need to make changes below this point
BIT_FILE=$(ATOMFPGA)/working/AtomBusMon.bit
BMM_FILE=$(ATOMFPGA)/src/AtomBusMon_bd.bmm
BIT_FILE=$(ATOMFPGA)/$(WORKING_DIR)/AtomBusMon.bit
BMM_FILE=$(ATOMFPGA)/$(SRC_DIR)/AtomBusMon_bd.bmm
# Papilio dev environment
PROG=${PAPILIO_LOADER}/linux32/papilio-prog
BSCAN=${PAPILIO_LOADER}/bscan_spi_xc3s500e.bit
SREC_CAT=srec_cat
GAWK=gawk
DATA2MEM=${XILINX}/ISE_DS/ISE/bin/lin/data2mem

10
firmware/Makefile.6809cpu
View File

@ -1,18 +1,20 @@
# Paths that will need changing
# default to the xc3s250e part
WORKING_DIR=working/250
SRC_DIR=src/250
ATOMFPGA=$(HOME)/atom/AtomBusMon
PAPILIO_LOADER=/opt/GadgetFactory/papilio-loader/programmer
XILINX=/opt/Xilinx/14.7
# Shouldn't need to make changes below this point
BIT_FILE=$(ATOMFPGA)/working/MC6809ECpuMon.bit
BMM_FILE=$(ATOMFPGA)/src/MC6809ECpuMon_bd.bmm
BIT_FILE=$(ATOMFPGA)/$(WORKING_DIR)/MC6809ECpuMon.bit
BMM_FILE=$(ATOMFPGA)/$(SRC_DIR)/MC6809ECpuMon_bd.bmm
# Papilio dev environment
PROG=${PAPILIO_LOADER}/linux32/papilio-prog
BSCAN=${PAPILIO_LOADER}/bscan_spi_xc3s500e.bit
SREC_CAT=srec_cat
GAWK=gawk
DATA2MEM=${XILINX}/ISE_DS/ISE/bin/lin/data2mem

10
firmware/Makefile.z80cpu
View File

@ -1,18 +1,20 @@
# Paths that will need changing
# default to the xc3s250e part
WORKING_DIR=working/250
SRC_DIR=src/250
ATOMFPGA=$(HOME)/atom/AtomBusMon
PAPILIO_LOADER=/opt/GadgetFactory/papilio-loader/programmer
XILINX=/opt/Xilinx/14.7
# Shouldn't need to make changes below this point
BIT_FILE=$(ATOMFPGA)/working/Z80CpuMon.bit
BMM_FILE=$(ATOMFPGA)/src/Z80CpuMon_bd.bmm
BIT_FILE=$(ATOMFPGA)/$(WORKING_DIR)/Z80CpuMon.bit
BMM_FILE=$(ATOMFPGA)/$(SRC_DIR)/Z80CpuMon_bd.bmm
# Papilio dev environment
PROG=${PAPILIO_LOADER}/linux32/papilio-prog
BSCAN=${PAPILIO_LOADER}/bscan_spi_xc3s500e.bit
SREC_CAT=srec_cat
GAWK=gawk
DATA2MEM=${XILINX}/ISE_DS/ISE/bin/lin/data2mem

14
gen_mcs.sh
View File

@ -1,11 +1,15 @@
#!/bin/bash
# Base defaults to 250, but can be passed in
BASE=${1:-250}
DESIGNS="6502cpu 6502fast 6502mon z80cpu 6809cpu"
DATE=$(date +"%Y%m%d_%H%M")
VERSION=$(grep "define VERSION" firmware/AtomBusMon.c | cut -d\" -f2)
DIR=releases/$VERSION/$DATE
DIR=releases/$BASE/$VERSION/$DATE/
echo "Building release in: "$DIR
mkdir -p $DIR
@ -15,20 +19,22 @@ pushd firmware
for i in $DESIGNS
do
make -f Makefile.$i clean
make -f Makefile.$i
make -f Makefile.$i SRC_DIR=src/${BASE} WORKING_DIR=working/${BASE}
ls -l *.bit
done
# Create a .MCS file and move to releases directory
. /opt/Xilinx/14.7/ISE_DS/settings*.sh
# . /opt/Xilinx/14.7/ISE_DS/settings*.sh
for i in $DESIGNS
do
NAME=avr${i}
promgen -u 0 $NAME.bit -o $NAME.mcs -p mcs -w -spi -s 8192
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/promgen -u 0 $NAME.bit -o $NAME.mcs -p mcs -w -spi -s 8192
mv $NAME.mcs ../$DIR
rm -f $NAME.bit $NAME.cfi $NAME.prm
done
popd
echo "Built release in: "$DIR
ls -lt $DIR

0
releases/0.72/20160713_1419/avr6502cpu.mcs → releases/250/0.72/20160713_1419/avr6502cpu.mcs
View File

0
releases/0.72/20160713_1419/avr6502fast.mcs → releases/250/0.72/20160713_1419/avr6502fast.mcs
View File

0
releases/0.72/20160713_1419/avr6502mon.mcs → releases/250/0.72/20160713_1419/avr6502mon.mcs
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0
releases/0.72/20160713_1419/avr6809cpu.mcs → releases/250/0.72/20160713_1419/avr6809cpu.mcs
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0
releases/0.72/20160713_1419/avrz80cpu.mcs → releases/250/0.72/20160713_1419/avrz80cpu.mcs
View File

0
releases/0.73/20160908_1449/avr6502cpu.mcs → releases/250/0.73/20160908_1449/avr6502cpu.mcs
View File

0
releases/0.73/20160908_1449/avr6502fast.mcs → releases/250/0.73/20160908_1449/avr6502fast.mcs
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0
releases/0.73/20160908_1449/avr6502mon.mcs → releases/250/0.73/20160908_1449/avr6502mon.mcs
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0
releases/0.73/20160908_1449/avr6809cpu.mcs → releases/250/0.73/20160908_1449/avr6809cpu.mcs
View File

0
releases/0.73/20160908_1449/avrz80cpu.mcs → releases/250/0.73/20160908_1449/avrz80cpu.mcs
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0
releases/Blank.bit → releases/250/Blank.bit
View File

0
releases/Blank.mcs → releases/250/Blank.mcs
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BIN
releases/500/Blank.bit Normal file
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Binary file not shown.

17742
releases/500/Blank.mcs Normal file
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File diff suppressed because it is too large Load Diff

0
src/AtomBusMon.bmm → src/250/AtomBusMon.bmm
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0
src/AtomCpuMon.bmm → src/250/AtomCpuMon.bmm
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0
src/AtomFast6502.bmm → src/250/AtomFast6502.bmm
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0
src/MC6809ECpuMon.bmm → src/250/MC6809ECpuMon.bmm
View File

0
src/XPM_Generic.bmm → src/250/XPM_Generic.bmm
View File

0
src/Z80CpuMon.bmm → src/250/Z80CpuMon.bmm
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38
src/500/AtomBusMon.bmm Normal file
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@ -0,0 +1,38 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

38
src/500/AtomCpuMon.bmm Normal file
View File

@ -0,0 +1,38 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

38
src/500/AtomFast6502.bmm Normal file
View File

@ -0,0 +1,38 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

42
src/500/MC6809ECpuMon.bmm Normal file
View File

@ -0,0 +1,42 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

17
src/500/XPM_Generic.bmm Normal file
View File

@ -0,0 +1,17 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/Mram_RAM8 [15:14];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM7 [13:12];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM6 [11:10];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM5 [ 9: 8];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM4 [ 7: 6];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM3 [ 5: 4];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM2 [ 3: 2];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM1 [ 1: 0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

42
src/500/Z80CpuMon.bmm Normal file
View File

@ -0,0 +1,42 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;