mirror of
https://github.com/hoglet67/AtomBusMon.git
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z80: updated T80 to version 350
Copyright (c) 2018 Sorgelig Taken from https://github.com/EisernSchild/t80/commit/cbaa6450b Changes I needed to make afterwards: 1. Fixup T80_Pack.vhd (missing params) 2. Replace T80a.vhd with my own version Change-Id: I275153ffbddb0d9d5b2d8b1fdc2109468cafb256
This commit is contained in:
David Banks
parent
975ba22848
commit
f710f7a20f
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@ -1,20 +1,23 @@
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#include "AtomBusMon.h"
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#define OFFSET_REG_BC 32
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#define OFFSET_REG_DE 34
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#define OFFSET_REG_HL 36
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#define OFFSET_REG_IX 38
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#define OFFSET_REG_BCp 40
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#define OFFSET_REG_DEp 42
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#define OFFSET_REG_HLp 44
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#define OFFSET_REG_IY 46
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#define OFFSET_REG_AF 48
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#define OFFSET_REG_AFp 50
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#define OFFSET_REG_SP 52
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#define OFFSET_REG_PC 54
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#define OFFSET_REG_I 56
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#define OFFSET_REG_R 57
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#define OFFSET_REG_IFF 58
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// Version 350 of T80 exposes the registers in this order (bit 211..bit 0):
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// IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
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#define OFFSET_REG_AF (32 + 0)
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#define OFFSET_REG_AFp (32 + 2)
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#define OFFSET_REG_I (32 + 4)
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#define OFFSET_REG_R (32 + 5)
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#define OFFSET_REG_SP (32 + 6)
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#define OFFSET_REG_PC (32 + 8)
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#define OFFSET_REG_BC (32 + 10)
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#define OFFSET_REG_DE (32 + 12)
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#define OFFSET_REG_HL (32 + 14)
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#define OFFSET_REG_IX (32 + 16)
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#define OFFSET_REG_BCp (32 + 18)
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#define OFFSET_REG_DEp (32 + 20)
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#define OFFSET_REG_HLp (32 + 22)
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#define OFFSET_REG_IY (32 + 24)
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#define OFFSET_REG_IFF (32 + 26)
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char statusString[8] = "SZIH-P-C";
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@ -32,14 +35,18 @@ void doCmdRegs(char *params) {
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hwRead16(OFFSET_REG_BCp),
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hwRead16(OFFSET_REG_DEp),
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hwRead16(OFFSET_REG_HLp));
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log0(" IX=%04X IY=%04X PC=%04X SP=%04X I=%02X R=%02X IFF=%02X\n",
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int iff2_iff1_im = hwRead8(OFFSET_REG_IFF) & 15;
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log0(" IX=%04X IY=%04X PC=%04X SP=%04X I=%02X R=%02X IM=%X IFF1=%X IFF2=%X\n",
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hwRead16(OFFSET_REG_IX),
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hwRead16(OFFSET_REG_IY),
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hwRead16(OFFSET_REG_PC),
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hwRead16(OFFSET_REG_SP),
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hwRead8(OFFSET_REG_I),
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hwRead8(OFFSET_REG_R),
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hwRead8(OFFSET_REG_IFF));
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(iff2_iff1_im & 3),
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(iff2_iff1_im >> 2) & 1,
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(iff2_iff1_im >> 3) & 1
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);
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char *sp = statusString;
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log0(" Status: ");
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for (i = 0; i <= 7; i++) {
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2114
src/T80/T80.vhd
2114
src/T80/T80.vhd
File diff suppressed because it is too large
Load Diff
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@ -1,10 +1,26 @@
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--------------------------------------------------------------------------------
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-- ****
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-- T80(c) core. Attempt to finish all undocumented features and provide
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-- accurate timings.
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-- Version 350.
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-- Copyright (c) 2018 Sorgelig
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-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
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-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
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-- correct implementation is still unclear.
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--
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-- ****
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-- T80(b) core. In an effort to merge and maintain bug fixes ....
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--
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-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
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-- Ver 300 started tidyup
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-- MikeJ March 2005
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-- Latest version from www.fpgaarcade.com (original www.opencores.org)
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--
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-- ****
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-- Z80 compatible microprocessor core
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--
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-- Version : 0247
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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@ -38,23 +54,17 @@
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t80/
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-- http://www.opencores.org/cvsweb.shtml/t80/
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--
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-- Limitations :
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--
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-- File history :
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--
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-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
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--
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-- 0238 : Fixed zero flag for 16 bit SBC and ADC
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--
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-- 0240 : Added GB operations
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--
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-- 0242 : Cleanup
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--
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-- 0247 : Cleanup
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--
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-- 0249 : add undocumented XY-Flags for CPI/CPD by TobiFlex 22.07.2012
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-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
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-- 0238 : Fixed zero flag for 16 bit SBC and ADC
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-- 0240 : Added GB operations
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-- 0242 : Cleanup
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-- 0247 : Cleanup
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--
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library IEEE;
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@ -62,301 +72,305 @@ use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity T80_ALU is
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generic(
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Mode : integer := 0;
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Flag_C : integer := 0;
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Flag_N : integer := 1;
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Flag_P : integer := 2;
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Flag_X : integer := 3;
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Flag_H : integer := 4;
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Flag_Y : integer := 5;
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Flag_Z : integer := 6;
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Flag_S : integer := 7
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);
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port(
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Arith16 : in std_logic;
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Z16 : in std_logic;
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ALU_cpi : in std_logic;
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ALU_Op : in std_logic_vector(3 downto 0);
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IR : in std_logic_vector(5 downto 0);
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ISet : in std_logic_vector(1 downto 0);
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BusA : in std_logic_vector(7 downto 0);
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BusB : in std_logic_vector(7 downto 0);
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F_In : in std_logic_vector(7 downto 0);
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Q : out std_logic_vector(7 downto 0);
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F_Out : out std_logic_vector(7 downto 0)
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);
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generic(
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Mode : integer := 0;
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Flag_C : integer := 0;
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Flag_N : integer := 1;
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Flag_P : integer := 2;
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Flag_X : integer := 3;
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Flag_H : integer := 4;
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Flag_Y : integer := 5;
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Flag_Z : integer := 6;
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Flag_S : integer := 7
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);
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port(
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Arith16 : in std_logic;
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Z16 : in std_logic;
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WZ : in std_logic_vector(15 downto 0);
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XY_State : in std_logic_vector(1 downto 0);
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ALU_Op : in std_logic_vector(3 downto 0);
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IR : in std_logic_vector(5 downto 0);
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ISet : in std_logic_vector(1 downto 0);
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BusA : in std_logic_vector(7 downto 0);
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BusB : in std_logic_vector(7 downto 0);
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F_In : in std_logic_vector(7 downto 0);
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Q : out std_logic_vector(7 downto 0);
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F_Out : out std_logic_vector(7 downto 0)
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);
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end T80_ALU;
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architecture rtl of T80_ALU is
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procedure AddSub(A : std_logic_vector;
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B : std_logic_vector;
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Sub : std_logic;
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Carry_In : std_logic;
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signal Res : out std_logic_vector;
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signal Carry : out std_logic) is
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variable B_i : unsigned(A'length - 1 downto 0);
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variable Res_i : unsigned(A'length + 1 downto 0);
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begin
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if Sub = '1' then
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B_i := not unsigned(B);
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else
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B_i := unsigned(B);
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end if;
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Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
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Carry <= Res_i(A'length + 1);
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Res <= std_logic_vector(Res_i(A'length downto 1));
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end;
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procedure AddSub(A : std_logic_vector;
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B : std_logic_vector;
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Sub : std_logic;
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Carry_In : std_logic;
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signal Res : out std_logic_vector;
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signal Carry : out std_logic) is
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-- AddSub variables (temporary signals)
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signal UseCarry : std_logic;
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signal Carry7_v : std_logic;
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signal Overflow_v : std_logic;
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signal HalfCarry_v : std_logic;
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signal Carry_v : std_logic;
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signal Q_v : std_logic_vector(7 downto 0);
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signal Q_cpi : std_logic_vector(4 downto 0);
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variable B_i : unsigned(A'length - 1 downto 0);
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variable Res_i : unsigned(A'length + 1 downto 0);
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begin
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if Sub = '1' then
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B_i := not unsigned(B);
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else
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B_i := unsigned(B);
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end if;
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signal BitMask : std_logic_vector(7 downto 0);
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Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
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Carry <= Res_i(A'length + 1);
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Res <= std_logic_vector(Res_i(A'length downto 1));
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end;
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-- AddSub variables (temporary signals)
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signal UseCarry : std_logic;
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signal Carry7_v : std_logic;
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signal Overflow_v : std_logic;
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signal HalfCarry_v : std_logic;
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signal Carry_v : std_logic;
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signal Q_v : std_logic_vector(7 downto 0);
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signal BitMask : std_logic_vector(7 downto 0);
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begin
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with IR(5 downto 3) select BitMask <= "00000001" when "000",
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"00000010" when "001",
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"00000100" when "010",
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"00001000" when "011",
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"00010000" when "100",
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"00100000" when "101",
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"01000000" when "110",
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"10000000" when others;
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with IR(5 downto 3) select BitMask <= "00000001" when "000",
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"00000010" when "001",
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"00000100" when "010",
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"00001000" when "011",
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"00010000" when "100",
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"00100000" when "101",
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"01000000" when "110",
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"10000000" when others;
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UseCarry <= not ALU_Op(2) and ALU_Op(0);
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AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
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AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
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AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
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OverFlow_v <= Carry_v xor Carry7_v;
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AddSub(BusA(3 downto 0), BusB(3 downto 0), '1', HalfCarry_v, Q_cpi(3 downto 0), Q_cpi(4));
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process (Arith16, ALU_OP, ALU_cpi, F_In, BusA, BusB, IR, Q_v, Q_cpi, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
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variable Q_t : std_logic_vector(7 downto 0);
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variable DAA_Q : unsigned(8 downto 0);
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begin
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Q_t := "--------";
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F_Out <= F_In;
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DAA_Q := "---------";
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case ALU_Op is
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when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
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F_Out(Flag_N) <= '0';
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F_Out(Flag_C) <= '0';
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case ALU_OP(2 downto 0) is
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when "000" | "001" => -- ADD, ADC
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Q_t := Q_v;
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F_Out(Flag_C) <= Carry_v;
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F_Out(Flag_H) <= HalfCarry_v;
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F_Out(Flag_P) <= OverFlow_v;
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when "010" | "011" | "111" => -- SUB, SBC, CP
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Q_t := Q_v;
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F_Out(Flag_N) <= '1';
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F_Out(Flag_C) <= not Carry_v;
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F_Out(Flag_H) <= not HalfCarry_v;
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F_Out(Flag_P) <= OverFlow_v;
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when "100" => -- AND
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Q_t(7 downto 0) := BusA and BusB;
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F_Out(Flag_H) <= '1';
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when "101" => -- XOR
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Q_t(7 downto 0) := BusA xor BusB;
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F_Out(Flag_H) <= '0';
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when others => -- OR "110"
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Q_t(7 downto 0) := BusA or BusB;
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F_Out(Flag_H) <= '0';
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end case;
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if ALU_Op(2 downto 0) = "111" then -- CP
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if ALU_cpi='1' then --CPI
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F_Out(Flag_X) <= Q_cpi(3);
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F_Out(Flag_Y) <= Q_cpi(1);
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else
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F_Out(Flag_X) <= BusB(3);
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F_Out(Flag_Y) <= BusB(5);
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end if;
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else
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F_Out(Flag_X) <= Q_t(3);
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F_Out(Flag_Y) <= Q_t(5);
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end if;
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if Q_t(7 downto 0) = "00000000" then
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F_Out(Flag_Z) <= '1';
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if Z16 = '1' then
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F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
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end if;
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else
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F_Out(Flag_Z) <= '0';
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end if;
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F_Out(Flag_S) <= Q_t(7);
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case ALU_Op(2 downto 0) is
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when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
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when others =>
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F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
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Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
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end case;
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if Arith16 = '1' then
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F_Out(Flag_S) <= F_In(Flag_S);
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F_Out(Flag_Z) <= F_In(Flag_Z);
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F_Out(Flag_P) <= F_In(Flag_P);
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end if;
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when "1100" =>
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-- DAA
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F_Out(Flag_H) <= F_In(Flag_H);
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F_Out(Flag_C) <= F_In(Flag_C);
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DAA_Q(7 downto 0) := unsigned(BusA);
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DAA_Q(8) := '0';
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if F_In(Flag_N) = '0' then
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-- After addition
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-- Alow > 9 or H = 1
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if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
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if (DAA_Q(3 downto 0) > 9) then
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F_Out(Flag_H) <= '1';
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else
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F_Out(Flag_H) <= '0';
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end if;
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DAA_Q := DAA_Q + 6;
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end if;
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-- new Ahigh > 9 or C = 1
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if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
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DAA_Q := DAA_Q + 96; -- 0x60
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end if;
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else
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-- After subtraction
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if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
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if DAA_Q(3 downto 0) > 5 then
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F_Out(Flag_H) <= '0';
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end if;
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DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
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end if;
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if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
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DAA_Q := DAA_Q - 352; -- 0x160
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end if;
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end if;
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F_Out(Flag_X) <= DAA_Q(3);
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F_Out(Flag_Y) <= DAA_Q(5);
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F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
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Q_t := std_logic_vector(DAA_Q(7 downto 0));
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if DAA_Q(7 downto 0) = "00000000" then
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F_Out(Flag_Z) <= '1';
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else
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F_Out(Flag_Z) <= '0';
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end if;
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F_Out(Flag_S) <= DAA_Q(7);
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F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
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DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
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when "1101" | "1110" =>
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-- RLD, RRD
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Q_t(7 downto 4) := BusA(7 downto 4);
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if ALU_Op(0) = '1' then
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Q_t(3 downto 0) := BusB(7 downto 4);
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else
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Q_t(3 downto 0) := BusB(3 downto 0);
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end if;
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F_Out(Flag_H) <= '0';
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F_Out(Flag_N) <= '0';
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F_Out(Flag_X) <= Q_t(3);
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F_Out(Flag_Y) <= Q_t(5);
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if Q_t(7 downto 0) = "00000000" then
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F_Out(Flag_Z) <= '1';
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else
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F_Out(Flag_Z) <= '0';
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end if;
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F_Out(Flag_S) <= Q_t(7);
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F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
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Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
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when "1001" =>
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-- BIT
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Q_t(7 downto 0) := BusB and BitMask;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
F_Out(Flag_P) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
F_Out(Flag_P) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_H) <= '1';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= '0';
|
||||
F_Out(Flag_Y) <= '0';
|
||||
if IR(2 downto 0) /= "110" then
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
end if;
|
||||
when "1010" =>
|
||||
-- SET
|
||||
Q_t(7 downto 0) := BusB or BitMask;
|
||||
when "1011" =>
|
||||
-- RES
|
||||
Q_t(7 downto 0) := BusB and not BitMask;
|
||||
when "1000" =>
|
||||
-- ROT
|
||||
case IR(5 downto 3) is
|
||||
when "000" => -- RLC
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "010" => -- RL
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "001" => -- RRC
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(0);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "011" => -- RR
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "100" => -- SLA
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '0';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "110" => -- SLL (Undocumented) / SWAP
|
||||
if Mode = 3 then
|
||||
Q_t(7 downto 4) := BusA(3 downto 0);
|
||||
Q_t(3 downto 0) := BusA(7 downto 4);
|
||||
F_Out(Flag_C) <= '0';
|
||||
else
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '1';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
end if;
|
||||
when "101" => -- SRA
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when others => -- SRL
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := '0';
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
end case;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
if ISet = "00" then
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
Q <= Q_t;
|
||||
end process;
|
||||
UseCarry <= not ALU_Op(2) and ALU_Op(0);
|
||||
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
|
||||
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
|
||||
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
|
||||
|
||||
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
|
||||
process (Carry_v, Carry7_v, Q_v)
|
||||
begin
|
||||
if(Mode=2) then
|
||||
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
|
||||
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
|
||||
OverFlow_v <= Carry_v xor Carry7_v;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, WZ, XY_State)
|
||||
variable Q_t : std_logic_vector(7 downto 0);
|
||||
variable DAA_Q : unsigned(8 downto 0);
|
||||
begin
|
||||
Q_t := "--------";
|
||||
F_Out <= F_In;
|
||||
DAA_Q := "---------";
|
||||
case ALU_Op is
|
||||
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_C) <= '0';
|
||||
case ALU_OP(2 downto 0) is
|
||||
when "000" | "001" => -- ADD, ADC
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_C) <= Carry_v;
|
||||
F_Out(Flag_H) <= HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "010" | "011" | "111" => -- SUB, SBC, CP
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_N) <= '1';
|
||||
F_Out(Flag_C) <= not Carry_v;
|
||||
F_Out(Flag_H) <= not HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "100" => -- AND
|
||||
Q_t(7 downto 0) := BusA and BusB;
|
||||
F_Out(Flag_H) <= '1';
|
||||
when "101" => -- XOR
|
||||
Q_t(7 downto 0) := BusA xor BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
when others => -- OR "110"
|
||||
Q_t(7 downto 0) := BusA or BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
end case;
|
||||
if ALU_Op(2 downto 0) = "111" then -- CP
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
else
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
end if;
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
if Z16 = '1' then
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
|
||||
end if;
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
case ALU_Op(2 downto 0) is
|
||||
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
|
||||
when others =>
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
end case;
|
||||
if Arith16 = '1' then
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
end if;
|
||||
when "1100" =>
|
||||
-- DAA
|
||||
F_Out(Flag_H) <= F_In(Flag_H);
|
||||
F_Out(Flag_C) <= F_In(Flag_C);
|
||||
DAA_Q(7 downto 0) := unsigned(BusA);
|
||||
DAA_Q(8) := '0';
|
||||
if F_In(Flag_N) = '0' then
|
||||
-- After addition
|
||||
-- Alow > 9 or H = 1
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if (DAA_Q(3 downto 0) > 9) then
|
||||
F_Out(Flag_H) <= '1';
|
||||
else
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q := DAA_Q + 6;
|
||||
end if;
|
||||
-- new Ahigh > 9 or C = 1
|
||||
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q + 96; -- 0x60
|
||||
end if;
|
||||
else
|
||||
-- After subtraction
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if DAA_Q(3 downto 0) > 5 then
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
|
||||
end if;
|
||||
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q - 352; -- 0x160
|
||||
end if;
|
||||
end if;
|
||||
F_Out(Flag_X) <= DAA_Q(3);
|
||||
F_Out(Flag_Y) <= DAA_Q(5);
|
||||
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
|
||||
Q_t := std_logic_vector(DAA_Q(7 downto 0));
|
||||
if DAA_Q(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= DAA_Q(7);
|
||||
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
|
||||
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
|
||||
when "1101" | "1110" =>
|
||||
-- RLD, RRD
|
||||
Q_t(7 downto 4) := BusA(7 downto 4);
|
||||
if ALU_Op(0) = '1' then
|
||||
Q_t(3 downto 0) := BusB(7 downto 4);
|
||||
else
|
||||
Q_t(3 downto 0) := BusB(3 downto 0);
|
||||
end if;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
when "1001" =>
|
||||
-- BIT
|
||||
Q_t(7 downto 0) := BusB and BitMask;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
F_Out(Flag_P) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
F_Out(Flag_P) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_H) <= '1';
|
||||
F_Out(Flag_N) <= '0';
|
||||
if IR(2 downto 0) = "110" or XY_State /= "00" then
|
||||
F_Out(Flag_X) <= WZ(11);
|
||||
F_Out(Flag_Y) <= WZ(13);
|
||||
else
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
end if;
|
||||
when "1010" =>
|
||||
-- SET
|
||||
Q_t(7 downto 0) := BusB or BitMask;
|
||||
when "1011" =>
|
||||
-- RES
|
||||
Q_t(7 downto 0) := BusB and not BitMask;
|
||||
when "1000" =>
|
||||
-- ROT
|
||||
case IR(5 downto 3) is
|
||||
when "000" => -- RLC
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "010" => -- RL
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "001" => -- RRC
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(0);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "011" => -- RR
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "100" => -- SLA
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '0';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "110" => -- SLL (Undocumented) / SWAP
|
||||
if Mode = 3 then
|
||||
Q_t(7 downto 4) := BusA(3 downto 0);
|
||||
Q_t(3 downto 0) := BusA(7 downto 4);
|
||||
F_Out(Flag_C) <= '0';
|
||||
else
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '1';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
end if;
|
||||
when "101" => -- SRA
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when others => -- SRL
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := '0';
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
end case;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
if ISet = "00" then
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
Q <= Q_t;
|
||||
end process;
|
||||
end;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,3 +1,13 @@
|
|||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
|
|
@ -38,7 +48,7 @@
|
|||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
|
|
@ -50,165 +60,177 @@ use IEEE.std_logic_1164.all;
|
|||
|
||||
package T80_Pack is
|
||||
|
||||
component T80
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
IORQ : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DInst : in std_logic_vector(7 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0);
|
||||
MC : out std_logic_vector(2 downto 0);
|
||||
TS : out std_logic_vector(2 downto 0);
|
||||
IntCycle_n : out std_logic;
|
||||
IntE : out std_logic;
|
||||
Stop : out std_logic;
|
||||
Regs : out std_logic_vector(255 downto 0)
|
||||
);
|
||||
end component;
|
||||
constant aNone : std_logic_vector(2 downto 0) := "111";
|
||||
constant aBC : std_logic_vector(2 downto 0) := "000";
|
||||
constant aDE : std_logic_vector(2 downto 0) := "001";
|
||||
constant aXY : std_logic_vector(2 downto 0) := "010";
|
||||
constant aIOA : std_logic_vector(2 downto 0) := "100";
|
||||
constant aSP : std_logic_vector(2 downto 0) := "101";
|
||||
constant aZI : std_logic_vector(2 downto 0) := "110";
|
||||
|
||||
component T80_Reg
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0);
|
||||
RegFileData : out std_logic_vector(127 downto 0)
|
||||
);
|
||||
end component;
|
||||
component T80
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
IORQ : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DInst : in std_logic_vector(7 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0);
|
||||
MC : out std_logic_vector(2 downto 0);
|
||||
TS : out std_logic_vector(2 downto 0);
|
||||
IntCycle_n : out std_logic;
|
||||
IntE : out std_logic;
|
||||
Stop : out std_logic;
|
||||
REG : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
|
||||
DIRSet : in std_logic := '0';
|
||||
DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_MCode
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
MCycle : in std_logic_vector(2 downto 0);
|
||||
F : in std_logic_vector(7 downto 0);
|
||||
NMICycle : in std_logic;
|
||||
IntCycle : in std_logic;
|
||||
XY_State : in std_logic_vector(1 downto 0);
|
||||
MCycles : out std_logic_vector(2 downto 0);
|
||||
TStates : out std_logic_vector(2 downto 0);
|
||||
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
|
||||
Inc_PC : out std_logic;
|
||||
Inc_WZ : out std_logic;
|
||||
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
|
||||
Read_To_Reg : out std_logic;
|
||||
Read_To_Acc : out std_logic;
|
||||
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
|
||||
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
|
||||
ALU_Op : out std_logic_vector(3 downto 0);
|
||||
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
|
||||
ALU_cpi : out std_logic;
|
||||
Save_ALU : out std_logic;
|
||||
PreserveC : out std_logic;
|
||||
Arith16 : out std_logic;
|
||||
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
|
||||
IORQ : out std_logic;
|
||||
Jump : out std_logic;
|
||||
JumpE : out std_logic;
|
||||
JumpXY : out std_logic;
|
||||
Call : out std_logic;
|
||||
RstP : out std_logic;
|
||||
LDZ : out std_logic;
|
||||
LDW : out std_logic;
|
||||
LDSPHL : out std_logic;
|
||||
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
|
||||
ExchangeDH : out std_logic;
|
||||
ExchangeRp : out std_logic;
|
||||
ExchangeAF : out std_logic;
|
||||
ExchangeRS : out std_logic;
|
||||
I_DJNZ : out std_logic;
|
||||
I_CPL : out std_logic;
|
||||
I_CCF : out std_logic;
|
||||
I_SCF : out std_logic;
|
||||
I_RETN : out std_logic;
|
||||
I_BT : out std_logic;
|
||||
I_BC : out std_logic;
|
||||
I_BTR : out std_logic;
|
||||
I_RLD : out std_logic;
|
||||
I_RRD : out std_logic;
|
||||
I_INRC : out std_logic;
|
||||
SetDI : out std_logic;
|
||||
SetEI : out std_logic;
|
||||
IMode : out std_logic_vector(1 downto 0);
|
||||
Halt : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
XYbit_undoc : out std_logic
|
||||
);
|
||||
end component;
|
||||
component T80_Reg
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0);
|
||||
DOR : out std_logic_vector(127 downto 0);
|
||||
DIRSet : in std_logic;
|
||||
DIR : in std_logic_vector(127 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_ALU
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_cpi : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
component T80_MCode
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
MCycle : in std_logic_vector(2 downto 0);
|
||||
F : in std_logic_vector(7 downto 0);
|
||||
NMICycle : in std_logic;
|
||||
IntCycle : in std_logic;
|
||||
XY_State : in std_logic_vector(1 downto 0);
|
||||
MCycles : out std_logic_vector(2 downto 0);
|
||||
TStates : out std_logic_vector(2 downto 0);
|
||||
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
|
||||
Inc_PC : out std_logic;
|
||||
Inc_WZ : out std_logic;
|
||||
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
|
||||
Read_To_Reg : out std_logic;
|
||||
Read_To_Acc : out std_logic;
|
||||
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
|
||||
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
|
||||
ALU_Op : out std_logic_vector(3 downto 0);
|
||||
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
|
||||
Save_ALU : out std_logic;
|
||||
PreserveC : out std_logic;
|
||||
Arith16 : out std_logic;
|
||||
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
|
||||
IORQ : out std_logic;
|
||||
Jump : out std_logic;
|
||||
JumpE : out std_logic;
|
||||
JumpXY : out std_logic;
|
||||
Call : out std_logic;
|
||||
RstP : out std_logic;
|
||||
LDZ : out std_logic;
|
||||
LDW : out std_logic;
|
||||
LDSPHL : out std_logic;
|
||||
LDHLSP : out std_logic;
|
||||
ADDSPdd : out std_logic;
|
||||
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
|
||||
ExchangeDH : out std_logic;
|
||||
ExchangeRp : out std_logic;
|
||||
ExchangeAF : out std_logic;
|
||||
ExchangeRS : out std_logic;
|
||||
I_DJNZ : out std_logic;
|
||||
I_CPL : out std_logic;
|
||||
I_CCF : out std_logic;
|
||||
I_SCF : out std_logic;
|
||||
I_RETN : out std_logic;
|
||||
I_BT : out std_logic;
|
||||
I_BC : out std_logic;
|
||||
I_BTR : out std_logic;
|
||||
I_RLD : out std_logic;
|
||||
I_RRD : out std_logic;
|
||||
I_INRC : out std_logic;
|
||||
SetDI : out std_logic;
|
||||
SetEI : out std_logic;
|
||||
IMode : out std_logic_vector(1 downto 0);
|
||||
Halt : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
XYbit_undoc : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_ALU
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end;
|
||||
|
|
|
|||
|
|
@ -1,3 +1,22 @@
|
|||
--------------------------------------------------------------------------------
|
||||
-- ****
|
||||
-- T80(c) core. Attempt to finish all undocumented features and provide
|
||||
-- accurate timings.
|
||||
-- Version 350.
|
||||
-- Copyright (c) 2018 Sorgelig
|
||||
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
|
||||
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
|
||||
-- correct implementation is still unclear.
|
||||
--
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- T80 Registers, technology independent
|
||||
--
|
||||
|
|
@ -38,15 +57,15 @@
|
|||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t51/
|
||||
-- http://www.opencores.org/cvsweb.shtml/t51/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0242 : Initial release
|
||||
-- 0242 : Initial release
|
||||
--
|
||||
-- 0244 : Changed to single register file
|
||||
-- 0244 : Changed to single register file
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
|
|
@ -54,70 +73,80 @@ use IEEE.std_logic_1164.all;
|
|||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_Reg is
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0);
|
||||
RegFileData : out std_logic_vector(127 downto 0)
|
||||
);
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0);
|
||||
DOR : out std_logic_vector(127 downto 0);
|
||||
DIRSet : in std_logic;
|
||||
DIR : in std_logic_vector(127 downto 0)
|
||||
);
|
||||
end T80_Reg;
|
||||
|
||||
architecture rtl of T80_Reg is
|
||||
|
||||
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
|
||||
signal RegsH : Register_Image(0 to 7);
|
||||
signal RegsL : Register_Image(0 to 7);
|
||||
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
|
||||
signal RegsH : Register_Image(0 to 7);
|
||||
signal RegsL : Register_Image(0 to 7);
|
||||
|
||||
begin
|
||||
|
||||
RegFileData( 7 downto 0) <= RegsL(0);
|
||||
RegFileData( 15 downto 8) <= RegsH(0);
|
||||
RegFileData( 23 downto 16) <= RegsL(1);
|
||||
RegFileData( 31 downto 24) <= RegsH(1);
|
||||
RegFileData( 39 downto 32) <= RegsL(2);
|
||||
RegFileData( 47 downto 40) <= RegsH(2);
|
||||
RegFileData( 55 downto 48) <= RegsL(3);
|
||||
RegFileData( 63 downto 56) <= RegsH(3);
|
||||
RegFileData( 71 downto 64) <= RegsL(4);
|
||||
RegFileData( 79 downto 72) <= RegsH(4);
|
||||
RegFileData( 87 downto 80) <= RegsL(5);
|
||||
RegFileData( 95 downto 88) <= RegsH(5);
|
||||
RegFileData(103 downto 96) <= RegsL(6);
|
||||
RegFileData(111 downto 104) <= RegsH(6);
|
||||
RegFileData(119 downto 112) <= RegsL(7);
|
||||
RegFileData(127 downto 120) <= RegsH(7);
|
||||
process (Clk)
|
||||
begin
|
||||
if rising_edge(Clk) then
|
||||
if DIRSet = '1' then
|
||||
RegsL(0) <= DIR( 7 downto 0);
|
||||
RegsH(0) <= DIR( 15 downto 8);
|
||||
|
||||
process (Clk)
|
||||
begin
|
||||
if Clk'event and Clk = '1' then
|
||||
if CEN = '1' then
|
||||
if WEH = '1' then
|
||||
RegsH(to_integer(unsigned(AddrA))) <= DIH;
|
||||
end if;
|
||||
if WEL = '1' then
|
||||
RegsL(to_integer(unsigned(AddrA))) <= DIL;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
RegsL(1) <= DIR( 23 downto 16);
|
||||
RegsH(1) <= DIR( 31 downto 24);
|
||||
|
||||
DOAH <= RegsH(to_integer(unsigned(AddrA)));
|
||||
DOAL <= RegsL(to_integer(unsigned(AddrA)));
|
||||
DOBH <= RegsH(to_integer(unsigned(AddrB)));
|
||||
DOBL <= RegsL(to_integer(unsigned(AddrB)));
|
||||
DOCH <= RegsH(to_integer(unsigned(AddrC)));
|
||||
DOCL <= RegsL(to_integer(unsigned(AddrC)));
|
||||
RegsL(2) <= DIR( 39 downto 32);
|
||||
RegsH(2) <= DIR( 47 downto 40);
|
||||
|
||||
RegsL(3) <= DIR( 55 downto 48);
|
||||
RegsH(3) <= DIR( 63 downto 56);
|
||||
|
||||
RegsL(4) <= DIR( 71 downto 64);
|
||||
RegsH(4) <= DIR( 79 downto 72);
|
||||
|
||||
RegsL(5) <= DIR( 87 downto 80);
|
||||
RegsH(5) <= DIR( 95 downto 88);
|
||||
|
||||
RegsL(6) <= DIR(103 downto 96);
|
||||
RegsH(6) <= DIR(111 downto 104);
|
||||
|
||||
RegsL(7) <= DIR(119 downto 112);
|
||||
RegsH(7) <= DIR(127 downto 120);
|
||||
elsif CEN = '1' then
|
||||
if WEH = '1' then
|
||||
RegsH(to_integer(unsigned(AddrA))) <= DIH;
|
||||
end if;
|
||||
if WEL = '1' then
|
||||
RegsL(to_integer(unsigned(AddrA))) <= DIL;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DOAH <= RegsH(to_integer(unsigned(AddrA)));
|
||||
DOAL <= RegsL(to_integer(unsigned(AddrA)));
|
||||
DOBH <= RegsH(to_integer(unsigned(AddrB)));
|
||||
DOBL <= RegsL(to_integer(unsigned(AddrB)));
|
||||
DOCH <= RegsH(to_integer(unsigned(AddrC)));
|
||||
DOCL <= RegsL(to_integer(unsigned(AddrC)));
|
||||
DOR <= RegsH(7) & RegsL(7) & RegsH(6) & RegsL(6) & RegsH(5) & RegsL(5) & RegsH(4) & RegsL(4) & RegsH(3) & RegsL(3) & RegsH(2) & RegsL(2) & RegsH(1) & RegsL(1) & RegsH(0) & RegsL(0);
|
||||
|
||||
end;
|
||||
|
|
|
|||
|
|
@ -176,9 +176,14 @@ begin
|
|||
MC => MCycle,
|
||||
TS => TState,
|
||||
IntCycle_n => IntCycle_n,
|
||||
Regs => Regs
|
||||
REG => Regs(211 downto 0),
|
||||
DIRSet => '0',
|
||||
DIR => (others => '0')
|
||||
);
|
||||
|
||||
Regs(255 downto 212) <= (others => '0');
|
||||
|
||||
|
||||
process (CLK_n)
|
||||
begin
|
||||
if CLK_n'event and CLK_n = '0' then
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user