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39 lines
714 B
Verilog
39 lines
714 B
Verilog
module UnknownAdapter
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(
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input clock,
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input mode,
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input [3:0] id,
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output led1, // red
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output led2, // trig 1
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output led3, // trig 2
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output ld1,
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output ld2,
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output ld3,
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output ld4,
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output ld5,
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output ld6,
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output ld7,
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output ld8
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);
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reg [24:0] counter;
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always@(posedge clock) begin
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counter <= counter + 1;
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end
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assign led1 = counter[24];
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assign led2 = 1'b0;
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assign led3 = 1'b0;
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assign ld1 = counter[24];
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assign ld2 = 1'b0;
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assign ld3 = 1'b0;
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assign ld4 = mode;
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assign ld5 = id[3];
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assign ld6 = id[2];
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assign ld7 = id[1];
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assign ld8 = id[0];
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endmodule
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