248 lines
7.5 KiB
VHDL
248 lines
7.5 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (c) 2019 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : MC6808CpuMonGODIL.vhd
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-- /___/ /\ Timestamp : 24/10/2019
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: MC6808CpuMonGODIL
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--Device: XC3S250E/XC3S500E
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity MC6809CpuMonGODIL is
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generic (
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num_comparators : integer := 8; -- default value correct for GODIL
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avr_prog_mem_size : integer := 1024 * 9 -- default value correct for GODIL
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);
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port (
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clock49 : in std_logic;
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-- A locally generated test clock
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-- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
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-- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
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clock_test : out std_logic;
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-- 6809/6809E mode selection
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-- Jumper is between pins B1 and D1
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-- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
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-- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
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EMode_n : in std_logic;
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--6809 Signals
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PIN33 : inout std_logic;
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PIN34 : inout std_logic;
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PIN35 : inout std_logic;
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PIN36 : inout std_logic;
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PIN38 : inout std_logic;
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PIN39 : in std_logic;
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-- Signals common to both 6809 and 6809E
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RES_n : in std_logic;
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NMI_n : in std_logic;
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IRQ_n : in std_logic;
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FIRQ_n : in std_logic;
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HALT_n : in std_logic;
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BS : out std_logic;
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BA : out std_logic;
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R_W_n : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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Data : inout std_logic_vector(7 downto 0);
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- GODIL Switches
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sw1 : in std_logic;
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sw2 : in std_logic;
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-- GODIL LEDs
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led3 : out std_logic;
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led6 : out std_logic;
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led8 : out std_logic;
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-- OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic;
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-- Debugging signals
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test1 : out std_logic;
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test2 : out std_logic
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);
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end MC6809CpuMonGODIL;
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architecture behavioral of MC6809CpuMonGODIL is
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signal clk_count : std_logic_vector(1 downto 0);
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signal quadrature : std_logic_vector(1 downto 0);
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signal clock7_3728 : std_logic;
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signal sw_reset_avr : std_logic;
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signal sw_reset_cpu : std_logic;
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signal led_bkpt : std_logic;
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signal led_trig0 : std_logic;
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signal led_trig1 : std_logic;
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signal E : std_logic;
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signal Q : std_logic;
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signal DMA_n_BREQ_n : std_logic;
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signal MRDY : std_logic;
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signal TSC : std_logic;
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signal LIC : std_logic;
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signal AVMA : std_logic;
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signal BUSY : std_logic;
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signal XTAL : std_logic;
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signal EXTAL : std_logic;
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begin
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-- Generics allows polarity of switches/LEDs to be tweaked from the project file
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sw_reset_cpu <= sw1;
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sw_reset_avr <= not sw2;
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led3 <= not led_trig0;
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led6 <= not led_trig1;
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led8 <= not led_bkpt;
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wrapper : entity work.MC6809CpuMon
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generic map (
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ClkMult => 10,
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ClkDiv => 31,
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ClkPer => 20.345,
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num_comparators => num_comparators,
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avr_prog_mem_size => avr_prog_mem_size
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)
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port map (
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-- Fast clock
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clock => clock49,
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-- Quadrature clocks
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E => E,
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Q => Q,
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--6809 Signals
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DMA_n_BREQ_n => DMA_n_BREQ_n,
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-- 6809E Sig
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TSC => TSC,
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LIC => LIC,
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AVMA => AVMA,
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BUSY => BUSY,
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-- Signals common to both 6809 and 6809E
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RES_n => RES_n,
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NMI_n => NMI_n,
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IRQ_n => IRQ_n,
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FIRQ_n => FIRQ_n,
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HALT_n => HALT_n,
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BS => BS,
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BA => BA,
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R_W_n => R_W_n,
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Addr => Addr,
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Data => Data,
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-- External trigger inputs
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trig => trig,
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-- Serial Console
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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-- Switches
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sw_reset_cpu => sw_reset_cpu,
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sw_reset_avr => sw_reset_avr,
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-- LEDs
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led_bkpt => led_bkpt,
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led_trig0 => led_trig0,
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led_trig1 => led_trig1,
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-- OHO_DY1 connected to test connector
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk,
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-- Debugging signals
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test1 => test1,
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test2 => test2
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);
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-- Pins whose functions are dependent on "E" mode
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PIN33 <= BUSY when EMode_n = '0' else 'Z';
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DMA_n_BREQ_n <= '1' when EMode_n = '0' else PIN33;
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PIN34 <= 'Z' when EMode_n = '0' else E;
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E <= PIN34 when EMode_n = '0' else quadrature(1);
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PIN35 <= 'Z' when EMode_n = '0' else Q;
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Q <= PIN35 when EMode_n = '0' else quadrature(0);
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PIN36 <= AVMA when EMode_n = '0' else 'Z';
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MRDY <= '1' when EMode_n = '0' else PIN36;
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PIN38 <= LIC when EMode_n = '0' else 'Z';
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EXTAL <= '0' when EMode_n = '0' else PIN38;
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TSC <= PIN39 when EMode_n = '0' else '0';
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XTAL <= '0' when EMode_n = '0' else PIN39;
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-- A locally generated test clock
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-- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
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-- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
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clock_test <= clk_count(1) when EMode_n = '0' else clock7_3728;
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-- Quadrature clock generator, unused in 6809E mode
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quadrature_gen : process(EXTAL)
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begin
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if rising_edge(EXTAL) then
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if (MRDY = '1') then
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if (quadrature = "00") then
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quadrature <= "01";
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elsif (quadrature = "01") then
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quadrature <= "11";
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elsif (quadrature = "11") then
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quadrature <= "10";
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else
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quadrature <= "00";
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end if;
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end if;
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end if;
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end process;
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-- Seperate piece of circuitry that emits a 7.3728MHz clock
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inst_dcm1 : entity work.DCM1 port map(
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CLKIN_IN => clock49,
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CLK0_OUT => clock7_3728,
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CLK0_OUT1 => open,
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CLK2X_OUT => open
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);
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clk_gen : process(clock7_3728)
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begin
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if rising_edge(clock7_3728) then
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clk_count <= clk_count + 1;
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end if;
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end process;
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end behavioral;
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