145 lines
4.2 KiB
VHDL
145 lines
4.2 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (c) 2019 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : MOS6502CpuMonLX9.vhd
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-- /___/ /\ Timestamp : 03/11/2019
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: MOS6502CpuMonLX9
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--Device: XC6SLX9
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--
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-- Note: in 65C02 mode, BE, ML_n and VP_n are not implemented
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity MOS6502CpuMonLX9 is
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generic (
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UseT65Core : boolean := true;
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UseAlanDCore : boolean := false;
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num_comparators : integer := 8;
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avr_prog_mem_size : integer := 8 * 1024
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);
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port (
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clock : in std_logic;
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-- 6502 Signals
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Phi0 : in std_logic;
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Phi1 : out std_logic;
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Phi2 : out std_logic;
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IRQ_n : in std_logic;
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NMI_n : in std_logic;
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Sync : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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R_W_n : out std_logic;
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Data : inout std_logic_vector(7 downto 0);
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SO_n : in std_logic;
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Res_n : in std_logic;
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Rdy : in std_logic;
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- Jumpers
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fakeTube_n : in std_logic;
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- Switches
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sw1 : in std_logic;
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sw2 : in std_logic;
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-- LEDs
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led3 : out std_logic;
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led6 : out std_logic;
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led8 : out std_logic;
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-- OHO_DY1 LED display
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic
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);
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end MOS6502CpuMonLX9;
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architecture behavioral of MOS6502CpuMonLX9 is
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signal sw_reset_cpu : std_logic;
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signal sw_reset_avr : std_logic;
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signal led_bkpt : std_logic;
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signal led_trig0 : std_logic;
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signal led_trig1 : std_logic;
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begin
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sw_reset_cpu <= sw1;
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sw_reset_avr <= sw2;
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led8 <= led_bkpt;
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led3 <= led_trig0;
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led6 <= led_trig1;
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wrapper : entity work.MOS6502CpuMon
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generic map (
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UseT65Core => UseT65Core,
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UseAlanDCore => UseAlanDCore,
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ClkMult => 8,
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ClkDiv => 25,
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ClkPer => 20.000,
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num_comparators => num_comparators,
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avr_prog_mem_size => avr_prog_mem_size
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)
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port map (
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clock => clock,
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-- 6502 Signals
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Phi0 => Phi0,
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Phi1 => Phi1,
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Phi2 => Phi2,
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IRQ_n => IRQ_n,
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NMI_n => NMI_n,
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Sync => Sync,
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Addr => Addr,
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R_W_n => R_W_n,
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Data => Data,
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SO_n => SO_n,
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Res_n => Res_n,
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Rdy => Rdy,
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-- External trigger inputs
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trig => trig,
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-- Jumpers
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fakeTube_n => fakeTube_n,
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-- Serial Console
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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-- Switches
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sw_reset_cpu => sw_reset_cpu,
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sw_reset_avr => sw_reset_avr,
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-- LEDs
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led_bkpt => led_bkpt,
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led_trig0 => led_trig0,
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led_trig1 => led_trig1,
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-- OHO_DY1 LED display
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk
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);
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end behavioral;
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