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336 lines
11 KiB
VHDL
336 lines
11 KiB
VHDL
--
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-- Z80 compatible microprocessor core, asynchronous top level
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--
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-- Version : 0247a
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t80/
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--
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-- Limitations :
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--
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-- File history :
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--
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-- 0208 : First complete release
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--
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-- 0211 : Fixed interrupt cycle
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--
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-- 0235 : Updated for T80 interface change
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--
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-- 0238 : Updated for T80 interface change
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--
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-- 0240 : Updated for T80 interface change
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--
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-- 0242 : Updated for T80 interface change
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--
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-- 0247 : Fixed bus req/ack cycle
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--
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-- 0247a: 7th of September, 2003 by Kazuhiro Tsujikawa (tujikawa@hat.hi-ho.ne.jp)
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-- Fixed IORQ_n, RD_n, WR_n bus timing
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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entity T80a is
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generic(
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Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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);
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port(
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-- Additions
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TS : out std_logic_vector(2 downto 0);
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Regs : out std_logic_vector(255 downto 0);
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PdcData : out std_logic_vector(7 downto 0);
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-- Original Signals
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RESET_n : in std_logic;
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CLK_n : in std_logic;
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CEN : in std_logic;
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WAIT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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MREQ_n : out std_logic;
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IORQ_n : out std_logic;
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RD_n : out std_logic;
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WR_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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A : out std_logic_vector(15 downto 0);
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Din : in std_logic_vector(7 downto 0);
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Dout : out std_logic_vector(7 downto 0);
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Den : out std_logic
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);
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end T80a;
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architecture rtl of T80a is
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signal Reset_s : std_logic;
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signal IntCycle_n : std_logic;
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signal NMICycle_n : std_logic;
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signal IORQ : std_logic;
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signal NoRead : std_logic;
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signal Write : std_logic;
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signal MREQ : std_logic;
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signal MReq_Inhibit : std_logic;
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signal IReq_Inhibit : std_logic; -- 0247a
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signal Req_Inhibit : std_logic;
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signal RD : std_logic;
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signal MREQ_n_i : std_logic;
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signal IORQ_n_i : std_logic;
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signal RD_n_i : std_logic;
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signal WR_n_i : std_logic;
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signal WR_n_j : std_logic; -- 0247a
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signal RFSH_n_i : std_logic;
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signal BUSAK_n_i : std_logic;
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signal A_i : std_logic_vector(15 downto 0);
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signal DO : std_logic_vector(7 downto 0);
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signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
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signal Wait_s : std_logic;
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signal MCycle : std_logic_vector(2 downto 0);
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signal TState : std_logic_vector(2 downto 0);
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signal HALT_n_int : std_logic;
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signal iack1 : std_logic;
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signal iack2 : std_logic;
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begin
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BUSAK_n <= BUSAK_n_i;
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MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
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RD_n_i <= not RD or (IORQ and IReq_Inhibit) or Req_Inhibit; -- DMB
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WR_n_j <= WR_n_i or (IORQ and IReq_Inhibit); -- DMB
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HALT_n <= HALT_n_int;
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--Remove tristate as in ICE-Z80 this is implmeneted in Z80CpuMon
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--MREQ_n <= MREQ_n_i; when BUSAK_n_i = '1' else 'Z';
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--IORQ_n <= IORQ_n_i or IReq_Inhibit when BUSAK_n_i = '1' else 'Z'; -- 0247a
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--RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
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--WR_n <= WR_n_j when BUSAK_n_i = '1' else 'Z'; -- 0247a
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--RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
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--A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
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MREQ_n <= MREQ_n_i;
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IORQ_n <= IORQ_n_i or IReq_Inhibit or Req_inhibit; --DMB
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RD_n <= RD_n_i;
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WR_n <= WR_n_j; -- 0247a
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RFSH_n <= RFSH_n_i;
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A <= A_i;
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Dout <= DO;
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Den <= Write and BUSAK_n_i;
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process (RESET_n, CLK_n)
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begin
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if RESET_n = '0' then
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Reset_s <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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Reset_s <= '1';
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end if;
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end process;
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u0 : T80
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generic map(
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Mode => Mode,
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IOWait => 1)
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port map(
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CEN => CEN,
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M1_n => M1_n,
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IORQ => IORQ,
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NoRead => NoRead,
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Write => Write,
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RFSH_n => RFSH_n_i,
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HALT_n => HALT_n_int,
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WAIT_n => Wait_s,
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INT_n => INT_n,
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NMI_n => NMI_n,
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RESET_n => Reset_s,
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BUSRQ_n => BUSRQ_n,
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BUSAK_n => BUSAK_n_i,
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CLK_n => CLK_n,
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A => A_i,
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DInst => Din,
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DI => DI_Reg,
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DO => DO,
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MC => MCycle,
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TS => TState,
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IntCycle_n => IntCycle_n,
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NMICycle_n => NMICycle_n,
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REG => Regs(211 downto 0),
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DIRSet => '0',
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DIR => (others => '0')
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);
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Regs(255 downto 212) <= (others => '0');
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process (CLK_n)
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begin
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if CLK_n'event and CLK_n = '0' then
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if CEN = '1' then
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Wait_s <= WAIT_n or (IORQ_n_i and MREQ_n_i);
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if TState = "011" and BUSAK_n_i = '1' then
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DI_Reg <= to_x01(Din);
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end if;
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end if;
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end if;
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end process;
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process (CLK_n) -- 0247a
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begin
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if CLK_n'event and CLK_n = '1' then
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IReq_Inhibit <= (not IORQ) and IntCycle_n;
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end if;
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end process;
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process (Reset_s,CLK_n) -- 0247a
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begin
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if Reset_s = '0' then
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WR_n_i <= '1';
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elsif CLK_n'event and CLK_n = '0' then
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if CEN = '1' then
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if (IORQ = '0') then
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if TState = "010" then
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WR_n_i <= not Write;
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elsif Tstate = "011" then
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WR_n_i <= '1';
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end if;
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else
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if TState = "001" then -- DMB
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WR_n_i <= not Write;
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elsif Tstate = "011" then
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WR_n_i <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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process (Reset_s,CLK_n) -- 0247a
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begin
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if Reset_s = '0' then
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Req_Inhibit <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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if MCycle = "001" and TState = "010" and wait_s = '1' then
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Req_Inhibit <= '1';
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else
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Req_Inhibit <= '0';
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end if;
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end if;
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end if;
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end process;
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process (Reset_s,CLK_n)
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begin
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if Reset_s = '0' then
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MReq_Inhibit <= '0';
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elsif CLK_n'event and CLK_n = '0' then
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if CEN = '1' then
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if MCycle = "001" and TState = "010" then
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MReq_Inhibit <= '1';
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else
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MReq_Inhibit <= '0';
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end if;
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end if;
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end if;
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end process;
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process(Reset_s,CLK_n) -- 0247a
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begin
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if Reset_s = '0' then
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RD <= '0';
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IORQ_n_i <= '1';
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MREQ <= '0';
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iack1 <= '0';
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iack2 <= '0';
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elsif CLK_n'event and CLK_n = '0' then
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if CEN = '1' then
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if MCycle = "001" then
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if IntCycle_n = '1' then
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-- Normal M1 Cycle
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if TState = "001" then
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RD <= '1';
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MREQ <= '1';
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IORQ_n_i <= '1';
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end if;
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else
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-- Interupt Ack Cycle
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-- 5 T-states: T1 T1 (auto wait) T1 (auto wait) T2 T3
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-- Assert IORQ in middle of third T1
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if TState = "001" then
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iack1 <= '1';
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iack2 <= iack1;
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else
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iack1 <= '0';
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iack2 <= '0';
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end if;
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if iack2 = '1' then
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IORQ_n_i <= '0';
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end if;
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end if;
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if TState = "011" then
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RD <= '0';
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IORQ_n_i <= '1';
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MREQ <= '1';
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end if;
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if TState = "100" then
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MREQ <= '0';
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end if;
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else
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if TState = "001" and NoRead = '0' then
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IORQ_n_i <= not IORQ;
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MREQ <= not IORQ;
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RD <= not Write; -- DMB
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end if;
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if TState = "011" then
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RD <= '0';
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IORQ_n_i <= '1';
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MREQ <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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TS <= TState;
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PdcData <= (not HALT_n_int) & (not NMICycle_n) & (not IntCycle_n) & "00000";
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end;
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