211 lines
5.7 KiB
VHDL
211 lines
5.7 KiB
VHDL
-------------------------------------------------------------------------------
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-- Copyright (c) 2019 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : MOS6502CpuMon.vhd
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-- /___/ /\ Timestamp : 03/11/2019
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: MOS6502CpuMon
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--Device: multiple
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity MOS6502CpuMon is
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generic (
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UseT65Core : boolean;
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UseAlanDCore : boolean;
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ClkMult : integer;
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ClkDiv : integer;
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ClkPer : real;
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num_comparators : integer;
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avr_prog_mem_size : integer
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);
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port (
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clock : in std_logic;
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-- 6502 Signals
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Phi0 : in std_logic;
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Phi1 : out std_logic;
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Phi2 : out std_logic;
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IRQ_n : in std_logic;
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NMI_n : in std_logic;
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Sync : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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R_W_n : out std_logic;
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Data : inout std_logic_vector(7 downto 0);
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SO_n : in std_logic;
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Res_n : in std_logic;
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Rdy : in std_logic;
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- Jumpers
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fakeTube_n : in std_logic;
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- Switches
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sw_reset_cpu : in std_logic;
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sw_reset_avr : in std_logic;
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-- LEDs
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led_bkpt : out std_logic;
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led_trig0 : out std_logic;
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led_trig1 : out std_logic;
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-- OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic;
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-- Test connector signals
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test : inout std_logic_vector(3 downto 0)
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);
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end MOS6502CpuMon;
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architecture behavioral of MOS6502CpuMon is
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signal clock_avr : std_logic;
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signal Din : std_logic_vector(7 downto 0);
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signal Dout : std_logic_vector(7 downto 0);
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signal Rdy_latched : std_logic;
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signal IRQ_n_sync : std_logic;
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signal NMI_n_sync : std_logic;
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signal Addr_int : std_logic_vector(15 downto 0);
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signal R_W_n_int : std_logic;
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signal Phi0_a : std_logic;
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signal Phi0_b : std_logic;
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signal Phi0_c : std_logic;
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signal Phi0_d : std_logic;
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signal cpu_clk : std_logic;
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signal busmon_clk : std_logic;
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begin
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inst_dcm0 : entity work.DCM0
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generic map (
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ClkMult => ClkMult,
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ClkDiv => ClkDiv,
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ClkPer => ClkPer
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)
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port map(
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CLKIN_IN => clock,
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CLKFX_OUT => clock_avr
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);
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core : entity work.MOS6502CpuMonCore
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generic map (
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UseT65Core => UseT65Core,
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UseAlanDCore => UseAlanDCore,
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num_comparators => num_comparators,
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avr_prog_mem_size => avr_prog_mem_size
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)
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port map (
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clock_avr => clock_avr,
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busmon_clk => busmon_clk,
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busmon_clken => '1',
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cpu_clk => cpu_clk,
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cpu_clken => '1',
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IRQ_n => IRQ_n_sync,
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NMI_n => NMI_n_sync,
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Sync => Sync,
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Addr => Addr_int,
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R_W_n => R_W_n_int,
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Din => Din,
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Dout => Dout,
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SO_n => SO_n,
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Res_n => Res_n,
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Rdy => Rdy_latched,
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trig => trig,
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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sw_reset_cpu => sw_reset_cpu,
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sw_reset_avr => sw_reset_avr,
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led_bkpt => led_bkpt,
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led_trig0 => led_trig0,
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led_trig1 => led_trig1,
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk,
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test => test
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);
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sync_gen : process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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NMI_n_sync <= NMI_n;
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IRQ_n_sync <= IRQ_n;
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end if;
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end process;
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-- 6502: Sample Rdy on the rising edge of Phi0
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rdy_6502: if UseT65Core generate
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process(Phi0)
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begin
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if rising_edge(Phi0) then
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Rdy_latched <= Rdy;
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end if;
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end process;
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end generate;
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-- 65C02: Sample Rdy on the falling edge of Phi0
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rdy_65c02: if UseAlanDCore generate
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process(Phi0)
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begin
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if falling_edge(Phi0) then
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Rdy_latched <= Rdy;
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end if;
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end process;
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end generate;
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-- Sample Data on the falling edge of Phi0_a
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data_latch : process(Phi0_a)
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begin
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if falling_edge(Phi0_a) then
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if (fakeTube_n = '0' and Addr_int = x"FEE0") then
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Din <= x"FE";
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else
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Din <= Data;
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end if;
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end if;
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end process;
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Data <= Dout when Phi0_c = '1' and R_W_n_int = '0' else (others => 'Z');
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R_W_n <= R_W_n_int;
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Addr <= Addr_int;
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clk_gen : process(clock)
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begin
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if rising_edge(clock) then
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Phi0_a <= Phi0;
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Phi0_b <= Phi0_a;
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Phi0_c <= Phi0_b;
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Phi0_d <= Phi0_c;
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end if;
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end process;
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Phi1 <= not Phi0_b;
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Phi2 <= Phi0_b;
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cpu_clk <= not Phi0_d;
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busmon_clk <= Phi0_d;
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end behavioral;
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