David Banks cc1c8ba709 Multiboot: increase cclk to 26MHz ... Change-Id: I7bb6c17a582c7d283458bd7ed8a1bc2852bb73b3		2019-10-16 16:11:44 +01:00
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board.ucf	z80: CLK_n timing constraint now 8MHz	2019-10-15 11:45:51 +01:00
icez80.xise	Multiboot: increase cclk to 26MHz	2019-10-16 16:11:44 +01:00
Makefile	Updated lx9_dave/icez80 for active level shifter design	2019-09-20 15:34:34 +01:00
memory.bmm	Updated lx9_dave/icez80 for active level shifter design	2019-09-20 15:34:34 +01:00