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65 lines
1.4 KiB
VHDL
65 lines
1.4 KiB
VHDL
--**********************************************************************************************
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-- Frequency divider for AVR uC (40 MHz -> 4 MHz or 40 MHz -> 20 MHz)
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-- Version 1.52(Dust Inc version)
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-- Modified 16.01.2006
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use WORK.AVRuCPackage.all;
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entity FrqDiv is port(
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clk_in : in std_logic;
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clk_out : out std_logic
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);
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end FrqDiv;
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architecture RTL of FrqDiv is
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signal DivCnt : std_logic_vector(3 downto 0);
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signal clk_out_int : std_logic;
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constant Div2 : boolean := TRUE;
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begin
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-- Must be sequentially encoded
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DivideBy10:if not Div2 generate
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Gen:process(clk_in)
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begin
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if(clk_in='1' and clk_in'event) then -- Clock
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if(DivCnt=x"4") then DivCnt <= x"0";
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else DivCnt <= DivCnt + 1;
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end if;
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if(DivCnt=x"4") then clk_out_int <= not clk_out_int;
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end if;
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end if;
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end process;
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end generate;
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DivideBy10:if Div2 generate
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Gen:process(clk_in)
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begin
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if(clk_in='1' and clk_in'event) then -- Clock
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clk_out_int <= not clk_out_int;
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end if;
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end process;
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end generate;
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clk_out <= clk_out_int;
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end RTL;
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