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103 lines
4.2 KiB
VHDL
103 lines
4.2 KiB
VHDL
--**********************************************************************************************
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-- Components declarations for JTAG OCD and "Flash" Programmer
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-- Version 0.2A
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-- Modified 31.05.2006
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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package JTAGCompPack is
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component OCDProgTCK is port(
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-- JTAG related inputs/outputs
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TRSTn : in std_logic; -- Optional
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TMS : in std_logic;
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TCK : in std_logic;
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TDI : in std_logic;
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TDO : out std_logic;
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TDO_OE : out std_logic;
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-- From/To cp2 clock domain("Flash" programmer)
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FlEEPrgAdr : out std_logic_vector(15 downto 0);
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FlPrgRdData : in std_logic_vector(15 downto 0);
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EEPrgRdData : in std_logic_vector(7 downto 0);
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FlEEPrgWrData : out std_logic_vector(15 downto 0);
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ChipEraseStart : out std_logic;
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ChipEraseDone : in std_logic;
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ProgEnable : out std_logic;
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FlWrMStart : out std_logic; -- Multiple
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FlWrSStart : out std_logic; -- Single
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FlRdMStart : out std_logic; -- Multiple
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FlRdSStart : out std_logic; -- Single
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EEWrStart : out std_logic;
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EERdStart : out std_logic;
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TAPCtrlTLR : out std_logic; -- TAP Controller is in the Test-Logic/Reset state
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-- CPU reset
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jtag_rst : out std_logic
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);
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end component;
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component OCDProgcp2 is port(
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-- AVR Control
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ireset : in std_logic;
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cp2 : in std_logic;
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-- From/To TCK clock domain("Flash" programmer)
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FlEEPrgAdr : in std_logic_vector(15 downto 0);
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FlPrgRdData : out std_logic_vector(15 downto 0);
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EEPrgRdData : out std_logic_vector(7 downto 0);
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FlEEPrgWrData : in std_logic_vector(15 downto 0);
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ChipEraseStart : in std_logic;
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ChipEraseDone : out std_logic;
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ProgEnable : in std_logic;
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FlWrMStart : in std_logic; -- Multiple
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FlWrSStart : in std_logic; -- Single
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FlRdMStart : in std_logic; -- Multiple
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FlRdSStart : in std_logic; -- Single
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EEWrStart : in std_logic;
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EERdStart : in std_logic;
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TAPCtrlTLR : in std_logic; -- TAP Controller is in the Test-Logic/Reset state
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-- From the core
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PC : in std_logic_vector(15 downto 0);
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-- To the PM("Flash")
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pm_adr : out std_logic_vector(15 downto 0);
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pm_h_we : out std_logic;
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pm_l_we : out std_logic;
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pm_dout : in std_logic_vector(15 downto 0);
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pm_din : out std_logic_vector(15 downto 0);
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-- To the "EEPROM"
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EEPrgSel : out std_logic;
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EEAdr : out std_logic_vector(11 downto 0);
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EEWrData : out std_logic_vector(7 downto 0);
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EERdData : in std_logic_vector(7 downto 0);
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EEWr : out std_logic
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);
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end component;
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component Resync1b_cp2 is port(
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cp2 : in std_logic;
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DIn : in std_logic;
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DOut : out std_logic
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);
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end component;
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component Resync1b_TCK is port(
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TCK : in std_logic;
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DIn : in std_logic;
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DOut : out std_logic
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);
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end component;
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component Resync16b_TCK is port(
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TCK : in std_logic;
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DIn : in std_logic_vector(15 downto 0);
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DOut : out std_logic_vector(15 downto 0)
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);
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end component;
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end JTAGCompPack;
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