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38 lines
1.3 KiB
VHDL
38 lines
1.3 KiB
VHDL
--**********************************************************************************************
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-- Fuses/Lock bits and Calibration bytes for JTAG "Flash" Programmer
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-- Version 0.11
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-- Modified 19.05.2004
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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package JTAGDataPack is
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-- Extended Fuse Byte
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constant C_ExtFuseByte : std_logic_vector(7 downto 0) := x"FD"; -- x"00"
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-- Fuse High Byte
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constant C_HighFuseByte : std_logic_vector(7 downto 0) := x"19"; -- x"01"
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-- Fuse Low Byte
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constant C_LowFuseByte : std_logic_vector(7 downto 0) := x"E3"; -- x"00"
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-- Lock bits
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constant C_LockBits : std_logic_vector(7 downto 0) := x"FF";
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-- Signature Bytes(3 Bytes)
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constant C_SignByte1 : std_logic_vector(7 downto 0) := x"1E";
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constant C_SignByte2 : std_logic_vector(7 downto 0) := x"97";
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constant C_SignByte3 : std_logic_vector(7 downto 0) := x"02";
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-- Calibration Bytes(4 Bytes)
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constant C_CalibrByte1 : std_logic_vector(7 downto 0) := x"C1";
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constant C_CalibrByte2 : std_logic_vector(7 downto 0) := x"C2";
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constant C_CalibrByte3 : std_logic_vector(7 downto 0) := x"C3";
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constant C_CalibrByte4 : std_logic_vector(7 downto 0) := x"C4";
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end JTAGDataPack;
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