mirror of
https://github.com/hoglet67/AtomBusMon.git
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43df61cd06
Change-Id: Ic21b05ae8ecb828d32e55fe36be501800cfb3407
316 lines
10 KiB
VHDL
316 lines
10 KiB
VHDL
--**********************************************************************************************
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-- JTAG "Flash" programmer for AVR Core(cp2 Clock Domain)
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-- Version 0.5
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-- Modified 20.06.2006
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use WORK.JTAGPack.all;
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use WORK.AVRuCPackage.all;
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entity OCDProgcp2 is port(
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-- AVR Control
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ireset : in std_logic;
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cp2 : in std_logic;
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-- From/To TCK clock domain("Flash" programmer)
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FlEEPrgAdr : in std_logic_vector(15 downto 0);
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FlPrgRdData : out std_logic_vector(15 downto 0);
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EEPrgRdData : out std_logic_vector(7 downto 0);
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FlEEPrgWrData : in std_logic_vector(15 downto 0);
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ChipEraseStart : in std_logic;
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ChipEraseDone : out std_logic;
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ProgEnable : in std_logic;
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FlWrMStart : in std_logic; -- Multiple
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FlWrSStart : in std_logic; -- Single
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FlRdMStart : in std_logic; -- Multiple
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FlRdSStart : in std_logic; -- Single
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EEWrStart : in std_logic;
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EERdStart : in std_logic;
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TAPCtrlTLR : in std_logic; -- TAP Controller is in the Test-Logic/Reset state
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-- From the core
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PC : in std_logic_vector(15 downto 0);
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-- To the PM("Flash")
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pm_adr : out std_logic_vector(15 downto 0);
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pm_h_we : out std_logic;
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pm_l_we : out std_logic;
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pm_dout : in std_logic_vector(15 downto 0);
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pm_din : out std_logic_vector(15 downto 0);
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-- To the "EEPROM"
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EEPrgSel : out std_logic;
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EEAdr : out std_logic_vector(11 downto 0);
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EEWrData : out std_logic_vector(7 downto 0);
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EERdData : in std_logic_vector(7 downto 0);
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EEWr : out std_logic
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);
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end OCDProgcp2;
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architecture RTL of OCDProgcp2 is
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-- **********************************************************************************
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-- *************************** Programmer part *********************************************
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-- **********************************************************************************
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-- Edge detectors
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signal TAPCtrlTLRDel : std_logic; -- TAP Run-Test/Idle
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-- Chip Erase Start edge detector
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signal ChipEraseStartDel : std_logic;
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-- Flash Write Start(using Virtual Flash Page Load Register) edge detector
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signal FlWrMStartDel : std_logic;
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-- Flash Write Start(using Load Data Low(2d)/Load Data High(2e)) edge detector
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signal FlWrSStartDel : std_logic;
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-- Flash Read Start(using Virtual Flash Page Read Register) edge detector
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signal FlRdMStartDel : std_logic;
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-- Flash Read Start(using Load Data Low and High Byte(3d)) edge detector
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signal FlRdSStartDel : std_logic;
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-- "Flash" programmer state machines
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signal FlWrCnt : std_logic_vector(1 downto 0) ; -- Write
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signal FlRdCnt : std_logic_vector(1 downto 0) ; -- Read (Low andHigh bytes)
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signal FlRd_St : std_logic; -- "Flash" read(Latch data)
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-- "Flash" address and data registers
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signal FlashPrgAdrRg : std_logic_vector(15 downto 0); -- Address(Write/Read)
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signal FlashPrgDataRg : std_logic_vector(15 downto 0); -- Data(for Write)
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-- Output copies
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signal pm_h_we_Int : std_logic;
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signal pm_l_we_Int : std_logic;
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-- Chip erase
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signal ChipErase_St : std_logic;
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-- "EEPROM" support
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-- Edge detectors
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signal EEWrStartDel : std_logic;
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signal EERdStartDel : std_logic;
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-- EEPROM address and data registers
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signal EEPrgAdrRg : std_logic_vector(EEAdr'range); -- Address(Write/Read)
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signal EEPrgDataRg : std_logic_vector(EEWrData'range); -- Data(for Write)
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signal EEWr_Int : std_logic;
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-- EEPROM programmer state machines
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signal EEWrCnt : std_logic_vector(1 downto 0) ; -- Write
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signal EERdCnt : std_logic_vector(1 downto 0) ; -- Read
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signal EERd_St : std_logic;
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begin
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-- ***************************** Programmer part ********************************
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FlashWriteCntAndCtrl:process(cp2)
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begin
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if(cp2='1' and cp2'event) then -- Clock cp2(Rising edge)
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-- Edge detectors
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TAPCtrlTLRDel <= TAPCtrlTLR;
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FlWrMStartDel <= FlWrMStart;
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FlWrSStartDel <= FlWrSStart;
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-- Delay counter
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if(TAPCtrlTLR='1') then -- Reset counter
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FlWrCnt <= (others => '0');
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elsif((FlWrMStart='0' and FlWrMStartDel='1')or
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(FlWrSStart='0' and FlWrSStartDel='1')) then
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FlWrCnt <= "01";
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elsif(FlWrCnt/="00") then
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FlWrCnt <= FlWrCnt + 1;
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end if;
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-- Control
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if(TAPCtrlTLR='1') then -- Reset control signals
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pm_h_we_Int <= '0';
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pm_l_we_Int <= '0';
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else
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case pm_h_we_Int is
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when '0' =>
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if((ChipEraseStart='1' and ChipEraseStartDel='0') or FlWrCnt="11") then
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pm_h_we_Int <= '1';
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end if;
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when '1' =>
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if(ChipErase_St='0' or (ChipErase_St='1' and FlashPrgAdrRg=C_MaxEraseAdr)) then
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pm_h_we_Int <= '0';
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end if;
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when others => null;
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end case;
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case pm_l_we_Int is
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when '0' =>
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if((ChipEraseStart='1' and ChipEraseStartDel='0') or FlWrCnt="11") then
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pm_l_we_Int <= '1';
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end if;
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when '1' =>
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if(ChipErase_St='0' or (ChipErase_St='1' and FlashPrgAdrRg=C_MaxEraseAdr)) then
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pm_l_we_Int <= '0';
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end if;
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when others => null;
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end case;
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end if;
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-- Address (for Erase,Write and Read!!!)
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if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase -> Clear address counter
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FlashPrgAdrRg <= (others => '0');
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elsif(ChipErase_St='1') then -- Chip erase -> increment aaddress
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FlashPrgAdrRg <= FlashPrgAdrRg + 1;
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elsif(FlWrCnt="11" or FlRdCnt="11") then -- Normal mode
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FlashPrgAdrRg <= FlEEPrgAdr;
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end if;
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-- Data
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if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase
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FlashPrgDataRg <= (others => '1');
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elsif(FlWrCnt="11") then -- Write to flash
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FlashPrgDataRg <= FlEEPrgWrData;
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end if;
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-- EEPROM Address (for Erase,Write and Read!!!)
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if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase -> Clear address counter
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EEPrgAdrRg <= (others => '0');
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elsif(ChipErase_St='1') then -- Chip erase -> increment aaddress
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EEPrgAdrRg <= EEPrgAdrRg + 1;
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elsif(EEWrCnt="11" or EERdCnt="11") then -- Normal mode
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EEPrgAdrRg <= FlEEPrgAdr(EEPrgAdrRg'range);
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end if;
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-- EEPROM Data
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if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase
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EEPrgDataRg <= (others => '1');
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elsif(EEWrCnt="11") then -- Write to EEPROM
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EEPrgDataRg <= FlEEPrgWrData(EEPrgDataRg'range);
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end if;
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-- EEPROM Write
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case EEWr_Int is
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when '0' =>
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if((ChipEraseStart='1' and ChipEraseStartDel='0') or EEWrCnt="11") then
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EEWr_Int <= '1';
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end if;
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when '1' =>
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if(ChipErase_St='0' or (ChipErase_St='1' and FlashPrgAdrRg=C_MaxEraseAdr)) then
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EEWr_Int <= '0';
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end if;
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when others => EEWr_Int <= '0';
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end case;
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-- EEPROM Read state
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if(EERdCnt="11") then
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EERd_St <= '1';
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else
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EERd_St <= '0';
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end if;
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end if;
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end process;
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-- "Flash" write enables
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pm_l_we <= pm_l_we_Int;
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pm_h_we <= pm_h_we_Int;
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-- "Flash" data inputs
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pm_din <= FlashPrgDataRg;
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-- EEPROM
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EEAdr <= EEPrgAdrRg;
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EEWrData <= EEPrgDataRg;
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EEWr <= EEWr_Int;
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EEPrgSel <= ProgEnable; -- !!!TBD!!! (Add EESAVE)
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-- Flash read
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FlashReadCntAndCtrl:process(cp2)
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begin
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if(cp2='1' and cp2'event) then -- Clock cp2(Rising edge)
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-- Edge detectors
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FlRdMStartDel <= FlRdMStart;
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FlRdSStartDel <= FlRdSStart;
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-- EEPROM edge detectors
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EEWrStartDel <= EEWrStart;
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EERdStartDel <= EERdStart;
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-- Delay counter (for read)
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if(TAPCtrlTLR='1') then -- Reset counter
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FlRdCnt <= (others => '0');
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elsif((FlRdMStart='0' and FlRdMStartDel='1')or
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(FlRdSStart='0' and FlRdSStartDel='1')) then
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FlRdCnt <= "01";
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elsif(FlRdCnt/="00") then
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FlRdCnt <= FlRdCnt + 1;
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end if;
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if(FlRdCnt="11") then
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FlRd_St <= '1';
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else
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FlRd_St <= '0';
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end if;
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if(FlRd_St='1') then -- Latch read data
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FlPrgRdData <= pm_dout;
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end if;
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-- EEPROM Read delay counter
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if(TAPCtrlTLR='1') then -- Reset counter
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EERdCnt <= (others => '0');
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elsif(EERdStart='0' and EERdStartDel='1') then -- Falling edge
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EERdCnt <= "01";
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elsif(EERdCnt/="00") then
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EERdCnt <= EERdCnt + 1;
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end if;
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-- EEPROM Write delay counter
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if(TAPCtrlTLR='1') then -- Reset counter
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EEWrCnt <= (others => '0');
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elsif(EEWrStart='0' and EEWrStartDel='1') then -- Falling edge
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EEWrCnt <= "01";
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elsif(EEWrCnt/="00") then
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EEWrCnt <= EEWrCnt + 1;
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end if;
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-- EEPROM Read latch
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if(EERd_St='1') then
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EEPrgRdData <= EERdData;
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end if;
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end if;
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end process;
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-- Chip Erase
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ChipEraseState:process(cp2)
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begin
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if(cp2='1' and cp2'event) then -- Clock cp2(Rising edge)
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ChipEraseStartDel <= ChipEraseStart; -- Edge detector
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if (TAPCtrlTLR='1') then -- Reset
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ChipErase_St <= '0';
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else
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case ChipErase_St is
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when '0' =>
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if(ChipEraseStart='1' and ChipEraseStartDel='0') then -- Start of chip erase
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ChipErase_St <= '1';
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end if;
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when '1' =>
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if (FlashPrgAdrRg=C_MaxEraseAdr) then
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ChipErase_St <= '0';
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end if;
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when others => null;
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end case;
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end if;
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end if;
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end process;
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-- !!!TBD!!!
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ChipEraseDone <= not ChipErase_St;
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-- *************************** End of programmer part *******************************
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pm_adr <= FlashPrgAdrRg when (ProgEnable='1') else -- Programming Mode
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PC; -- Normal Operations
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end RTL;
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