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40 lines
1.0 KiB
VHDL
40 lines
1.0 KiB
VHDL
--**********************************************************************************************
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-- Resynchronizer(1 bit,TCK clock) for JTAG OCD and "Flash" controller
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-- Version 0.1
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-- Modified 27.05.2004
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity Resync1b_TCK is port(
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TCK : in std_logic;
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DIn : in std_logic;
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DOut : out std_logic
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);
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end Resync1b_TCK;
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architecture RTL of Resync1b_TCK is
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signal DIn_Tmp : std_logic;
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begin
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ResynchronizerStageOne:process(TCK)
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begin
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if(TCK='0' and TCK'event) then -- Clock(Falling edge)
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DIn_Tmp <= DIn; -- Stage 1
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end if;
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end process;
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ResynchronizerStageTwo:process(TCK)
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begin
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if(TCK='1' and TCK'event) then -- Clock(Rising edge)
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DOut <= DIn_Tmp; -- Stage 2
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end if;
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end process;
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end RTL;
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