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34 lines
896 B
VHDL
34 lines
896 B
VHDL
--**********************************************************************************************
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-- Resynchronizer(1 bit,cp2 clock) for JTAG OCD and "Flash" controller
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-- Version 0.1
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-- Modified 27.05.2004
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity Resync1b_cp2 is port(
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cp2 : in std_logic;
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DIn : in std_logic;
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DOut : out std_logic
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);
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end Resync1b_cp2;
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architecture RTL of Resync1b_cp2 is
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signal DIn_Tmp : std_logic;
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begin
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ResynchronizerDFFs:process(cp2)
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begin
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if(cp2='1' and cp2'event) then -- Clock
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DIn_Tmp <= DIn; -- Stage 1
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DOut <= DIn_Tmp; -- Stage 2
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end if;
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end process;
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end RTL;
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