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https://github.com/hoglet67/AtomBusMon.git
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106 lines
3.2 KiB
VHDL
106 lines
3.2 KiB
VHDL
--************************************************************************************************
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-- Arrbiter and Address/Data multiplexer for AVR core
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-- Version 0.2
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-- Designed by Ruslan Lepetenok
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-- Modified 27.07.2005
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--************************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use WORK.MemAccessCtrlPack.all;
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entity ArbiterAndMux is port(
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--Clock and reset
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ireset : in std_logic;
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cp2 : in std_logic;
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-- Bus masters
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busmin : in MastersOutBus_Type;
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busmwait : out std_logic_vector(CNumOfBusMasters-1 downto 0);
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-- Memory Address,Data and Control
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ramadr : out std_logic_vector(15 downto 0);
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ramdout : out std_logic_vector(7 downto 0);
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ramre : out std_logic;
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ramwe : out std_logic;
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cpuwait : in std_logic
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);
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end ArbiterAndMux;
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architecture RTL of ArbiterAndMux is
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signal sel_mast : std_logic_vector(CNumOfBusMasters-1 downto 0);
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signal sel_mast_rg : std_logic_vector(sel_mast'range);
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constant c_zero_vect : std_logic_vector(CNumOfBusMasters-1 downto 0) := (others => '0');
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begin
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StoreBusMNum:process(ireset,cp2)
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begin
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if (ireset='0') then -- Reset
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sel_mast_rg <= (others => '0');
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elsif (cp2='1' and cp2'event) then -- Clock
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if(cpuwait='1') then -- Store selected bus master number
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sel_mast_rg <= sel_mast;
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end if;
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end if;
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end process;
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-- Fixed priority arbitration
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ArbitrationComb:process(busmin) -- Combinatorial
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begin
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sel_mast <= (others => '0');
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for i in 0 to CNumOfBusMasters-1 loop
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if(busmin(i).ramre='1' or busmin(i).ramwe='1') then
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sel_mast(i) <= '1';
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exit;
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end if;
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end loop;
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end process;
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MuxComb:process(busmin,sel_mast,sel_mast_rg,cpuwait) -- Combinatorial
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begin
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ramadr <= (others => '0');
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ramdout <= (others => '0');
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ramre <= '0';
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ramwe <= '0';
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for i in 0 to CNumOfBusMasters-1 loop
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if(cpuwait='1') then
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if(sel_mast_rg(i)='1') then
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ramadr <= busmin(i).ramadr;
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ramdout <= busmin(i).dout;
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ramre <= busmin(i).ramre;
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ramwe <= busmin(i).ramwe;
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end if;
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else -- cpuwait='0'
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if(sel_mast(i)='1') then
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ramadr <= busmin(i).ramadr;
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ramdout <= busmin(i).dout;
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ramre <= busmin(i).ramre;
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ramwe <= busmin(i).ramwe;
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end if;
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end if;
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end loop;
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end process;
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WaitGenComb:process(cpuwait,busmin,sel_mast) -- Combinatorial
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begin
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busmwait <= (others => '0');
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if((busmin(busmwait'low).ramre='1' or busmin(busmwait'low).ramwe='1') and cpuwait='1') then
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busmwait(busmwait'low) <= '1';
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end if;
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for i in 1 to CNumOfBusMasters-1 loop
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if((busmin(i).ramre='1' or busmin(i).ramwe='1')and(sel_mast(i-1 downto 0)/=c_zero_vect(i-1 downto 0) or cpuwait='1')) then
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busmwait(i) <= '1';
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end if;
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end loop;
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end process;
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-- For the purpose of test only
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--ramdout(sel_mast'range) <= sel_mast;
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-- For the purpose of test only
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end RTL; |