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https://github.com/hoglet67/AtomBusMon.git
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60 lines
2.0 KiB
VHDL
60 lines
2.0 KiB
VHDL
-- *****************************************************************************************
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--
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-- Version 0.1
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-- Modified 24.07.2005
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-- Designed by Ruslan Lepetenok
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-- *****************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use WORK.MemAccessCtrlPack.all;
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package MemAccessCompPack is
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component ArbiterAndMux is port(
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--Clock and reset
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ireset : in std_logic;
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cp2 : in std_logic;
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-- Bus masters
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busmin : in MastersOutBus_Type;
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busmwait : out std_logic_vector(CNumOfBusMasters-1 downto 0);
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-- Memory Address,Data and Control
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ramadr : out std_logic_vector(15 downto 0);
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ramdout : out std_logic_vector(7 downto 0);
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ramre : out std_logic;
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ramwe : out std_logic;
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cpuwait : in std_logic
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);
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end component;
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component MemRdMux is port(
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slv_outs : in SlavesOutBus_Type;
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ram_sel : in std_logic; -- Data RAM selection(optional input)
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ram_dout : in std_logic_vector(7 downto 0); -- Data memory output
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dout : out std_logic_vector(7 downto 0) -- Data output
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);
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end component;
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component RAMAdrDcd is port(
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ramadr : in std_logic_vector(15 downto 0);
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ramre : in std_logic;
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ramwe : in std_logic;
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-- Memory mapped I/O i/f
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stb_IO : out std_logic;
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stb_IOmod : out std_logic_vector(CNumOfSlaves-1 downto 0);
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-- Data memory i/f
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ram_we : out std_logic;
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ram_ce : out std_logic;
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ram_sel : out std_logic
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);
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end component;
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end MemAccessCompPack;
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