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60 lines
1.9 KiB
VHDL
60 lines
1.9 KiB
VHDL
--************************************************************************************************
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-- Address decoder
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-- Version 0.11A
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-- Designed by Ruslan Lepetenok
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-- Modified 31.07.2005
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--************************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use WORK.MemAccessCtrlPack.all;
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entity RAMAdrDcd is port(
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ramadr : in std_logic_vector(15 downto 0);
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ramre : in std_logic;
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ramwe : in std_logic;
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-- Memory mapped I/O i/f
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stb_IO : out std_logic;
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stb_IOmod : out std_logic_vector(CNumOfSlaves-1 downto 0);
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-- Data memory i/f
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ram_we : out std_logic;
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ram_ce : out std_logic;
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ram_sel : out std_logic
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);
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end RAMAdrDcd;
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architecture RTL of RAMAdrDcd is
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signal ram_sel_int : std_logic;
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begin
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stb_IO <= '1' when (ramadr(ramadr'high downto ramadr'high-CMemMappedIOBaseAdr'high) = CMemMappedIOBaseAdr) else '0';
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--MMIOAdrDcd:process(ramadr)
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--begin
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-- stb_IOmod <= (others => '0');
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-- for i in 0 to CNumOfSlaves-1 loop
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-- if(ramadr(7 downto 4)=i) then
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-- stb_IOmod(i) <= '1';
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-- end if;
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-- end loop;
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--end process;
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-- For the purpose of test only
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--stb_IOmod(0) <= '1' when ramadr(15 downto 4)=x"017" else '0';
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--stb_IOmod(1) <= '1' when ramadr(15 downto 4)=x"018" else '0';
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stb_IOmod(0) <= '1' when ramadr(7 downto 4)=x"0" else '0';
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stb_IOmod(1) <= '1' when ramadr(7 downto 4)=x"1" else '0';
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-- For the purpose of test only
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-- RAM i/f
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ram_sel_int <= '1'when (ramadr(ramadr'high downto ramadr'high-CDRAMBaseAdr'high) = CDRAMBaseAdr) else '0';
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ram_sel <= ram_sel_int;
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ram_we <= ram_sel_int and ramwe;
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ram_ce <= ram_sel_int and (ramwe or ramre);
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end RTL;
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