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82 lines
2.7 KiB
VHDL
82 lines
2.7 KiB
VHDL
--************************************************************************************************
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-- 16Kx16(32 KB) PM RAM for AVR Core(Xilinx)
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-- Version 0.2
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-- Designed by Ruslan Lepetenok
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-- Modified 30.07.2005
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--************************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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-- For Synplicity Synplify
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--library virtexe;
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--use virtexe.components.all;
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-- Aldec
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library unisim;
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use unisim.vcomponents.all;
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entity XPM16Kx16 is port(
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cp2 : in std_logic;
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ce : in std_logic;
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address : in std_logic_vector(13 downto 0);
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din : in std_logic_vector(15 downto 0);
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dout : out std_logic_vector(15 downto 0);
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weh : in std_logic;
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wel : in std_logic
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);
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end XPM16Kx16;
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architecture RTL of XPM16Kx16 is
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type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range);
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signal RAMBlDOut : RAMBlDOut_Type;
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signal WEBL : std_logic_vector(2**(address'length-9)-1 downto 0);
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signal WEBH : std_logic_vector(2**(address'length-9)-1 downto 0);
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signal gnd : std_logic;
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begin
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gnd <= '0';
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WEBH_Dcd:for i in WEBL'range generate
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WEBL(i) <= '1' when (wel='1' and address(address'high downto 9)=i) else '0';
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end generate ;
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WEBL_Dcd:for i in WEBH'range generate
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WEBH(i) <= '1' when (weh='1' and address(address'high downto 9)=i) else '0';
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end generate ;
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RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
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RAM_ByteLow:component RAMB4_S8 port map(
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DO => RAMBlDOut(i)(7 downto 0),
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ADDR => address(8 downto 0),
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DI => din(7 downto 0),
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EN => ce,
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CLK => cp2,
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WE => WEBL(i),
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RST => gnd
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);
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RAM_ByteHigh:component RAMB4_S8 port map(
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DO => RAMBlDOut(i)(15 downto 8),
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ADDR => address(8 downto 0),
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DI => din(15 downto 8),
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EN => ce,
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CLK => cp2,
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WE => WEBH(i),
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RST => gnd
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);
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end generate;
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-- Output data mux
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dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
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end RTL;
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