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65 lines
2.0 KiB
VHDL
65 lines
2.0 KiB
VHDL
--**********************************************************************************************
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-- Resynchronizers
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-- Version 0.1
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-- Modified 10.01.2007
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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package rsnc_comp_pack is
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component rsnc_vect is generic(
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width : integer := 8;
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add_stgs_num : integer := 0;
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inv_f_stgs : integer := 0
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);
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port(
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clk : in std_logic;
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di : in std_logic_vector(width-1 downto 0);
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do : out std_logic_vector(width-1 downto 0)
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);
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end component;
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component rsnc_bit is generic(
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add_stgs_num : integer := 0;
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inv_f_stgs : integer := 0
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);
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port(
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clk : in std_logic;
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di : in std_logic;
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do : out std_logic
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);
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end component;
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component rsnc_l_vect is generic(
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tech : integer := 0;
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width : integer := 8;
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add_stgs_num : integer := 0
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);
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port(
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clk : in std_logic;
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di : in std_logic_vector(width-1 downto 0);
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do : out std_logic_vector(width-1 downto 0)
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);
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end component;
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component rsnc_l_bit is generic(
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tech : integer := 0;
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add_stgs_num : integer := 0
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);
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port(
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clk : in std_logic;
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di : in std_logic;
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do : out std_logic
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);
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end component;
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end rsnc_comp_pack;
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