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58 lines
1.6 KiB
VHDL
58 lines
1.6 KiB
VHDL
--**********************************************************************************************
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-- Resynchronizer (for bit) with latch
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-- Version 0.1
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-- Modified 10.01.2007
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity rsnc_l_bit is generic(
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tech : integer := 0;
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add_stgs_num : integer := 0
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);
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port(
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clk : in std_logic;
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di : in std_logic;
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do : out std_logic
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);
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end rsnc_l_bit;
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architecture rtl of rsnc_l_bit is
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type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic;
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signal rsnc_rg_current : rsnc_vect_type;
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signal rsnc_rg_next : rsnc_vect_type;
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begin
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-- Latch
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latch_prc:process(clk)
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begin
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if(clk='0') then -- Clock (falling edge)
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rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
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end if;
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end process;
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-- Latch
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seq_re_prc:process(clk)
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begin
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if(clk='1' and clk'event) then -- Clock (rising edge)
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rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1);
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end if;
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end process;
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comb_prc:process(di,rsnc_rg_current)
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begin
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rsnc_rg_next(0) <= di;
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for i in 1 to rsnc_rg_next'high loop
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rsnc_rg_next(i) <= rsnc_rg_current(i-1);
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end loop;
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end process;
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do <= rsnc_rg_current(rsnc_rg_current'high);
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end rtl;
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