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https://github.com/hoglet67/AtomBusMon.git
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43df61cd06
Change-Id: Ic21b05ae8ecb828d32e55fe36be501800cfb3407
71 lines
2.1 KiB
VHDL
71 lines
2.1 KiB
VHDL
--**********************************************************************************************
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-- SPI Peripheral for the AVR Core
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-- Version 1.2
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-- Modified 10.01.2007
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use WORK.std_library.all;
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use WORK.avr_adr_pack.all;
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entity spi_slv_sel is generic(num_of_slvs : integer := 7);
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port(
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-- AVR Control
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ireset : in std_logic;
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cp2 : in std_logic;
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adr : in std_logic_vector(15 downto 0);
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dbus_in : in std_logic_vector(7 downto 0);
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dbus_out : out std_logic_vector(7 downto 0);
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iore : in std_logic;
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iowe : in std_logic;
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out_en : out std_logic;
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-- Output
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slv_sel_n : out std_logic_vector(num_of_slvs-1 downto 0)
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);
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end spi_slv_sel;
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architecture RTL of spi_slv_sel is
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constant SPISlvDcd_Address : integer := PINF_Address;
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signal SlvSelRg_Current : std_logic_vector(num_of_slvs-1 downto 0);
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signal SlvSelRg_Next : std_logic_vector(num_of_slvs-1 downto 0);
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begin
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RegWrSeqPrc:process(ireset,cp2)
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begin
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if (ireset='0') then -- Reset
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SlvSelRg_Current <= (others => '0');
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elsif (cp2='1' and cp2'event) then -- Clock
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SlvSelRg_Current <= SlvSelRg_Next;
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end if;
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end process;
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RegWrComb:process(adr,iowe,dbus_in,SlvSelRg_Current)
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begin
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SlvSelRg_Next <= SlvSelRg_Current;
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if(fn_to_integer(adr)=SPISlvDcd_Address and iowe='1') then
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SlvSelRg_Next <= dbus_in(num_of_slvs-1 downto 0);
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end if;
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end process;
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slv_sel_n <= not SlvSelRg_Current(slv_sel_n'range);
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out_en <= '1' when (fn_to_integer(adr)=SPISlvDcd_Address and iore='1') else '0';
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dbus_out(num_of_slvs-1 downto 0) <= SlvSelRg_Current;
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UnusedBits:if(num_of_slvs<8) generate
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dbus_out(dbus_out'high downto num_of_slvs) <= (others => '0');
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end generate;
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end RTL;
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