mirror of
https://github.com/hoglet67/AtomBusMon.git
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351 lines
14 KiB
VHDL
351 lines
14 KiB
VHDL
--************************************************************************************************
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-- Component declarations for AVR core
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-- Version 2.6A
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-- Designed by Ruslan Lepetenok
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-- Modified 31.05.2006
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--************************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use WORK.AVRuCPackage.all;
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package AVR_uC_CompPack is
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component pport is generic(PPortNum : natural);
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port(
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-- AVR Control
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ireset : in std_logic;
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cp2 : in std_logic;
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adr : in std_logic_vector(15 downto 0);
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dbus_in : in std_logic_vector(7 downto 0);
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dbus_out : out std_logic_vector(7 downto 0);
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iore : in std_logic;
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iowe : in std_logic;
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out_en : out std_logic;
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-- External connection
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portx : out std_logic_vector(7 downto 0);
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ddrx : out std_logic_vector(7 downto 0);
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pinx : in std_logic_vector(7 downto 0);
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irqlines : out std_logic_vector(7 downto 0));
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end component;
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component external_mux is port (
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ramre : in std_logic;
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dbus_out : out std_logic_vector (7 downto 0);
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ram_data_out : in std_logic_vector (7 downto 0);
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io_port_bus : in ext_mux_din_type;
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io_port_en_bus : in ext_mux_en_type;
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irqack : in std_logic;
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irqackad : in std_logic_vector(4 downto 0);
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ind_irq_ack : out std_logic_vector(22 downto 0)
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);
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end component;
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component RAMDataReg is port(
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ireset : in std_logic;
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cp2 : in std_logic;
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cpuwait : in std_logic;
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RAMDataIn : in std_logic_vector(7 downto 0);
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RAMDataOut : out std_logic_vector(7 downto 0)
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);
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end component;
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component Timer_Counter is port(
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-- AVR Control
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ireset : in std_logic;
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cp2 : in std_logic;
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cp2en : in std_logic;
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tmr_cp2en : in std_logic;
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stopped_mode : in std_logic; -- ??
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tmr_running : in std_logic; -- ??
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adr : in std_logic_vector(15 downto 0);
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dbus_in : in std_logic_vector(7 downto 0);
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dbus_out : out std_logic_vector(7 downto 0);
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iore : in std_logic;
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iowe : in std_logic;
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out_en : out std_logic;
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-- External inputs/outputs
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EXT1 : in std_logic;
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EXT2 : in std_logic;
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OC0_PWM0 : out std_logic;
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OC1A_PWM1A : out std_logic;
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OC1B_PWM1B : out std_logic;
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OC2_PWM2 : out std_logic;
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-- Interrupt related signals
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TC0OvfIRQ : out std_logic;
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TC0OvfIRQ_Ack : in std_logic;
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TC0CmpIRQ : out std_logic;
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TC0CmpIRQ_Ack : in std_logic;
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TC2OvfIRQ : out std_logic;
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TC2OvfIRQ_Ack : in std_logic;
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TC2CmpIRQ : out std_logic;
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TC2CmpIRQ_Ack : in std_logic;
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TC1OvfIRQ : out std_logic;
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TC1OvfIRQ_Ack : in std_logic;
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TC1CmpAIRQ : out std_logic;
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TC1CmpAIRQ_Ack : in std_logic;
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TC1CmpBIRQ : out std_logic;
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TC1CmpBIRQ_Ack : in std_logic;
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TC1ICIRQ : out std_logic;
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TC1ICIRQ_Ack : in std_logic;
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--Status bits
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PWM2bit : out std_logic;
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PWM0bit : out std_logic;
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PWM10bit : out std_logic;
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PWM11bit : out std_logic
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);
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end component;
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COMPONENT ExtIRQ_Controller
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PORT(
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-- begin Signals required by AVR8 for this core, do not modify.
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nReset : in STD_LOGIC;
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clk : in STD_LOGIC;
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adr : in STD_LOGIC_VECTOR (15 downto 0);
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dbus_in : in STD_LOGIC_VECTOR (7 downto 0);
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dbus_out : out STD_LOGIC_VECTOR (7 downto 0);
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iore : in STD_LOGIC;
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iowe : in STD_LOGIC;
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out_en : out STD_LOGIC;
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-- end Signals required by AVR8 for this core, do not modify.
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clken : in STD_LOGIC;
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irq_clken : in STD_LOGIC;
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extpins : in STD_LOGIC_VECTOR(7 downto 0);
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INTx : out STD_LOGIC_VECTOR(7 downto 0)
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);
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END COMPONENT;
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----*************** UART ***************************
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--component uart is port(
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-- -- AVR Control
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-- ireset : in std_logic;
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-- cp2 : in std_logic;
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-- adr : in std_logic_vector(15 downto 0);
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-- dbus_in : in std_logic_vector(7 downto 0);
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-- dbus_out : out std_logic_vector(7 downto 0);
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-- iore : in std_logic;
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-- iowe : in std_logic;
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-- out_en : out std_logic;
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--
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-- --UART
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-- rxd : in std_logic;
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-- rx_en : out std_logic;
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-- txd : out std_logic;
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-- tx_en : out std_logic;
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--
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-- --IRQ
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-- txcirq : out std_logic;
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-- txc_irqack : in std_logic;
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-- udreirq : out std_logic;
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-- rxcirq : out std_logic);
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--end component;
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-- Core itself
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component AVR_Core is port(
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--Clock and reset
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cp2 : in std_logic;
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cp2en : in std_logic;
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ireset : in std_logic;
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-- JTAG OCD support
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valid_instr : out std_logic;
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insert_nop : in std_logic;
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block_irq : in std_logic;
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change_flow : out std_logic;
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-- Program Memory
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pc : out std_logic_vector (15 downto 0);
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inst : in std_logic_vector (15 downto 0);
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-- I/O control
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adr : out std_logic_vector (15 downto 0);
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iore : out std_logic;
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iowe : out std_logic;
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-- Data memory control
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ramadr : out std_logic_vector (15 downto 0);
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ramre : out std_logic;
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ramwe : out std_logic;
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cpuwait : in std_logic;
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-- Data paths
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dbusin : in std_logic_vector (7 downto 0);
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dbusout : out std_logic_vector (7 downto 0);
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-- Interrupt
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irqlines : in std_logic_vector (22 downto 0);
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irqack : out std_logic;
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irqackad : out std_logic_vector(4 downto 0);
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--Sleep Control
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sleepi : out std_logic;
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irqok : out std_logic;
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globint : out std_logic;
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--Watchdog
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wdri : out std_logic);
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end component;
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-- Reset generator
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component ResetGenerator is port(
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-- Clock inputs
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cp2 : in std_logic;
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cp64m : in std_logic;
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-- Reset inputs
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nrst : in std_logic;
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npwrrst : in std_logic;
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wdovf : in std_logic;
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jtagrst : in std_logic;
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-- Reset outputs
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nrst_cp2 : out std_logic;
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nrst_cp64m : out std_logic;
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nrst_clksw : out std_logic
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);
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end component;
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-- Components for the simulation only
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component PROM is port(
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address_in : in std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0));
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end component;
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component DataRAM is
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generic(RAMSize :positive);
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port (
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cp2 : in std_logic;
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address : in std_logic_vector (LOG2(RAMSize)-1 downto 0);
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ramwe : in std_logic;
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din : in std_logic_vector (7 downto 0);
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dout : out std_logic_vector (7 downto 0));
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end component;
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component CPUWaitGenerator is port(
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ireset : in std_logic;
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cp2 : in std_logic;
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ramre : in std_logic;
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ramwe : in std_logic;
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cpuwait : out std_logic
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);
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end component;
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component ClockSwitch is port(
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-- Reset
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ireset : in std_logic;
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-- Clock input and output
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cp2_In : in std_logic;
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cp2_Out : out std_logic;
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-- Control inputs
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sleepi : in std_logic;
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irqok : in std_logic;
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globint : in std_logic;
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sleep_en : in std_logic
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);
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end component;
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-- JTAG
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component JTAGOCDPrgTop is port(
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-- AVR Control
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ireset : in std_logic;
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cp2 : in std_logic;
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-- JTAG related inputs/outputs
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TRSTn : in std_logic; -- Optional
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TMS : in std_logic;
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TCK : in std_logic;
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TDI : in std_logic;
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TDO : out std_logic;
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TDO_OE : out std_logic;
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-- From the core
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PC : in std_logic_vector(15 downto 0);
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-- To the PM("Flash")
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pm_adr : out std_logic_vector(15 downto 0);
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pm_h_we : out std_logic;
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pm_l_we : out std_logic;
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pm_dout : in std_logic_vector(15 downto 0);
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pm_din : out std_logic_vector(15 downto 0);
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-- To the "EEPROM"
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EEPrgSel : out std_logic;
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EEAdr : out std_logic_vector(11 downto 0);
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EEWrData : out std_logic_vector(7 downto 0);
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EERdData : in std_logic_vector(7 downto 0);
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EEWr : out std_logic;
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-- CPU reset
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jtag_rst : out std_logic
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);
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end component;
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component uart is port(
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-- AVR Control
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ireset : in std_logic;
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cp2 : in std_logic;
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adr : in std_logic_vector(15 downto 0);
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dbus_in : in std_logic_vector(7 downto 0);
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dbus_out : out std_logic_vector(7 downto 0);
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iore : in std_logic;
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iowe : in std_logic;
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out_en : out std_logic;
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-- UART
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rxd : in std_logic;
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rx_en : out std_logic;
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txd : out std_logic;
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tx_en : out std_logic;
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-- IRQ
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txcirq : out std_logic;
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txc_irqack : in std_logic;
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udreirq : out std_logic;
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rxcirq : out std_logic
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);
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end component;
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-- SMBus
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--component SMBusMod is port(
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-- -- AVR Control
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-- ireset : in std_logic;
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-- cp2 : in std_logic;
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-- adr : in std_logic_vector(15 downto 0);
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-- dbus_in : in std_logic_vector(7 downto 0);
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-- dbus_out : out std_logic_vector(7 downto 0);
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-- iore : in std_logic;
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-- iowe : in std_logic;
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-- out_en : out std_logic;
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-- -- Slave IRQ
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-- twiirq : out std_logic;
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-- -- Master IRQ
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-- msmbirq : out std_logic;
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-- -- "Off state" timer IRQ
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-- offstirq : out std_logic;
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-- offstirq_ack : in std_logic;
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-- -- TRI control and data for the slave channel
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-- sdain : in std_logic;
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-- sdaout : out std_logic;
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-- sdaen : out std_logic;
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-- sclin : in std_logic;
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-- sclout : out std_logic;
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-- sclen : out std_logic;
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-- -- TRI control and data for the master channel
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-- msdain : in std_logic;
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-- msdaout : out std_logic;
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-- msdaen : out std_logic;
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-- msclin : in std_logic;
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-- msclout : out std_logic;
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-- msclen : out std_logic
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-- );
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--
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--end component;
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component FrqDiv is port(
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clk_in : in std_logic;
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clk_out : out std_logic
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);
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end component;
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end AVR_uC_CompPack;
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