mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-06-26 00:29:28 +00:00
162 lines
5.1 KiB
VHDL
162 lines
5.1 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (c) 2015 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : AtomBusMon.vhd
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-- /___/ /\ Timestamp : 30/05/2015
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: AtomBusMon
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--Device: XC3S250E
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity AtomBusMon is
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generic (
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LEDsActiveHigh : boolean := false; -- default value correct for GODIL
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SW1ActiveHigh : boolean := true; -- default value correct for GODIL
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SW2ActiveHigh : boolean := false; -- default value correct for GODIL
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ClkMult : integer := 10; -- default value correct for GODIL
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ClkDiv : integer := 31; -- default value correct for GODIL
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ClkPer : real := 20.345 -- default value correct for GODIL
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);
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port (
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clock49 : in std_logic;
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-- 6502 Signals
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Addr : in std_logic_vector(15 downto 0);
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Phi2 : in std_logic;
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RNW : in std_logic;
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Sync : in std_logic;
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Rdy : out std_logic;
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nRST : inout std_logic;
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- HD44780 LCD
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--lcd_rs : out std_logic;
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--lcd_rw : out std_logic;
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--lcd_e : out std_logic;
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--lcd_db : inout std_logic_vector(7 downto 4);
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-- AVR Serial Port
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- GODIL Switches
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sw1 : in std_logic;
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sw2 : in std_logic;
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-- GODIL LEDs
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led3 : out std_logic;
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led6 : out std_logic;
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led8 : out std_logic;
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-- OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic
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);
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end AtomBusMon;
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architecture behavioral of AtomBusMon is
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signal clock_avr : std_logic;
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signal Rdy_int : std_logic;
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signal nRSTin : std_logic;
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signal nRSTout : std_logic;
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signal led3_n : std_logic; -- led to indicate ext trig 0 is active
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signal led6_n : std_logic; -- led to indicate ext trig 1 is active
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signal led8_n : std_logic; -- led to indicate CPU has hit a breakpoint (and is stopped)
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signal sw_interrupt_n : std_logic; -- switch to pause the CPU
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signal sw_reset_n : std_logic; -- switch to reset the CPU
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begin
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-- Generics allows polarity of switches/LEDs to be tweaked from the project file
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sw_interrupt_n <= not sw1 when SW1ActiveHigh else sw1;
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sw_reset_n <= not sw2 when SW2ActiveHigh else sw2;
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led3 <= not led3_n when LEDsActiveHigh else led3_n;
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led6 <= not led6_n when LEDsActiveHigh else led6_n;
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led8 <= not led8_n when LEDsActiveHigh else led8_n;
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inst_dcm0 : entity work.DCM0
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generic map (
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ClkMult => ClkMult,
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ClkDiv => ClkDiv,
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ClkPer => ClkPer
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)
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port map(
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CLKIN_IN => clock49,
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CLKFX_OUT => clock_avr
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);
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mon : entity work.BusMonCore
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generic map (
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avr_prog_mem_size => 1024 * 8
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)
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port map (
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clock_avr => clock_avr,
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busmon_clk => Phi2,
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busmon_clken => '1',
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cpu_clk => not Phi2,
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cpu_clken => '1',
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Addr => Addr,
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Data => (others => '0'),
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Rd_n => not RNW,
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Wr_n => RNW,
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RdIO_n => '1',
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WrIO_n => '1',
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Sync => Sync,
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Rdy => Rdy_int,
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nRSTin => nRSTin,
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nRSTout => nRSTout,
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CountCycle => Rdy_int,
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Regs => (others => '0'),
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RdMemOut => open,
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WrMemOut => open,
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RdIOOut => open,
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WrIOOut => open,
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AddrOut => open,
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DataOut => open,
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DataIn => (others => '0'),
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Done => '1',
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trig => trig,
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lcd_rs => open,
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lcd_rw => open,
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lcd_e => open,
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lcd_db => open,
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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sw1 => not sw_interrupt_n,
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nsw2 => sw_reset_n,
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led3 => led3_n,
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led6 => led6_n,
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led8 => led8_n,
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk,
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SS_Step => open,
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SS_Single => open
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);
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Rdy <= Rdy_int;
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-- Tristate buffer driving reset back out
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nRSTin <= nRST;
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nRST <= '0' when nRSTout <= '0' else 'Z';
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end behavioral;
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