mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-06-26 00:29:28 +00:00
282 lines
9.0 KiB
VHDL
282 lines
9.0 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (c) 2015 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : AtomBusMon.vhd
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-- /___/ /\ Timestamp : 30/05/2015
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: AtomBusMon
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--Device: XC3S250E
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--
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-- This desing uses a DCM to generate a 16x internal clock from Phi0
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-- Output signals can be placed in units of 1/16th Phi0
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--
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-- There are two constraints to be aware of:
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--
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-- 1. There is no defined phase relationship between Phi0 and Phi1/2
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-- This is because Phi is typically too slow for a Spartan -6 DLL
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-- If the host system also uses Phi0, then this may cause problems.
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--
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-- 2. Phi0 must be a single frequency clock, or the DCM will not lock
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-- This will not, therefore, work in a Beeb because of the clock
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-- stretching when IO devices are accessed.
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--
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-- The Atom satisfies both of these constraints.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use work.OhoPack.all ;
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entity AtomFast6502 is
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generic (
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UseT65Core : boolean := true;
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UseAlanDCore : boolean := false;
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LEDsActiveHigh : boolean := false; -- default value correct for GODIL
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SW1ActiveHigh : boolean := true; -- default value correct for GODIL
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SW2ActiveHigh : boolean := false; -- default value correct for GODIL
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ClkMult : integer := 10; -- default value correct for GODIL
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ClkDiv : integer := 31; -- default value correct for GODIL
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ClkPer : real := 20.345 -- default value correct for GODIL
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);
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port (
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clock49 : in std_logic;
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-- 6502 Signals
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--Rdy : in std_logic;
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Phi0 : in std_logic;
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Phi1 : out std_logic;
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Phi2 : out std_logic;
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IRQ_n : in std_logic;
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NMI_n : in std_logic;
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Sync : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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R_W_n : out std_logic;
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Data : inout std_logic_vector(7 downto 0);
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SO_n : in std_logic;
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Res_n : inout std_logic;
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- GODIL Switches
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sw1 : in std_logic;
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sw2 : in std_logic;
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-- GODIL LEDs
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led3 : out std_logic;
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led6 : out std_logic;
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led8 : out std_logic;
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-- OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic
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);
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end AtomFast6502;
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architecture behavioral of AtomFast6502 is
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-- Clocking
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signal clock_avr : std_logic;
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signal clock_16x : std_logic;
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signal clk_div : std_logic_vector(3 downto 0);
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signal cpu_clken : std_logic;
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signal cpu_dataen : std_logic;
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signal busmon_clken : std_logic;
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-- DCM watchdog
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signal dcm_reset : std_logic;
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signal dcm_locked : std_logic;
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signal dcm_count : std_logic_vector(9 downto 0);
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signal edge0 : std_logic;
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signal edge1 : std_logic;
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signal Din : std_logic_vector(7 downto 0);
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signal Addr0 : std_logic_vector(15 downto 0);
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signal R_W_n0 : std_logic;
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signal Sync0 : std_logic;
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signal Dout0 : std_logic_vector(7 downto 0);
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signal Addr1 : std_logic_vector(15 downto 0);
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signal R_W_n1 : std_logic;
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signal Sync1 : std_logic;
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signal Dout1 : std_logic_vector(7 downto 0);
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signal IRQ_n_sync : std_logic;
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signal NMI_n_sync : std_logic;
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signal Res_n_in : std_logic;
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signal Res_n_out : std_logic;
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signal led3_n : std_logic; -- led to indicate ext trig 0 is active
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signal led6_n : std_logic; -- led to indicate ext trig 1 is active
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signal led8_n : std_logic; -- led to indicate CPU has hit a breakpoint (and is stopped)
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signal sw_interrupt_n : std_logic; -- switch to pause the CPU
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signal sw_reset_n : std_logic; -- switch to reset the CPU
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begin
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-- Generics allows polarity of switches/LEDs to be tweaked from the project file
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sw_interrupt_n <= not sw1 when SW1ActiveHigh else sw1;
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sw_reset_n <= not sw2 when SW2ActiveHigh else sw2;
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led3 <= not led3_n when LEDsActiveHigh else led3_n;
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led6 <= not led6_n when LEDsActiveHigh else led6_n;
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led8 <= not led8_n when LEDsActiveHigh else led8_n;
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inst_dcm0 : entity work.DCM0
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generic map (
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ClkMult => ClkMult,
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ClkDiv => ClkDiv,
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ClkPer => ClkPer
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)
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port map(
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CLKIN_IN => clock49,
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CLKFX_OUT => clock_avr
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);
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inst_dcm2 : entity work.DCM2 port map(
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CLKIN_IN => Phi0,
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CLKFX_OUT => clock_16x,
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LOCKED => dcm_locked,
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RESET => dcm_reset
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);
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core : entity work.MOS6502CpuMonCore
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generic map (
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UseT65Core => UseT65Core,
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UseAlanDCore => UseAlanDCore,
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avr_prog_mem_size => 1024 * 8
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)
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port map (
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clock_avr => clock_avr,
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busmon_clk => clock_16x,
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busmon_clken => busmon_clken,
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cpu_clk => clock_16x,
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cpu_clken => cpu_clken,
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IRQ_n => IRQ_n_sync,
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NMI_n => NMI_n_sync,
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Sync => Sync0,
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Addr => Addr0,
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R_W_n => R_W_n0,
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Din => Din,
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Dout => Dout0,
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SO_n => SO_n,
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Res_n_in => Res_n_in,
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Res_n_out => Res_n_out,
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Rdy => '1',
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trig => trig,
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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sw1 => not sw_interrupt_n,
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nsw2 => sw_reset_n,
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led3 => led3_n,
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led6 => led6_n,
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led8 => led8_n,
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk
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);
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-- Tristate buffer driving reset back out
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Res_n_in <= Res_n;
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Res_n <= '0' when Res_n_out <= '0' else 'Z';
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sync_gen : process(clock_16x)
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begin
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if rising_edge(clock_16x) then
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NMI_n_sync <= NMI_n;
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IRQ_n_sync <= IRQ_n;
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end if;
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end process;
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Addr <= Addr1;
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R_W_n <= R_W_n1;
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Sync <= Sync1;
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Data <= Dout1 when cpu_dataen = '1' and R_W_n1 = '0' else (others => 'Z');
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-- Din is registered in cpu_clken in BusMonCore
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Din <= Data;
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process(clock_16x)
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begin
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if rising_edge(clock_16x) then
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-- internal clock running 16x Phi0
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clk_div <= clk_div + 1;
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-- clock the CPU on cycle 0
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if (clk_div = "1111") then
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cpu_clken <= '1';
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else
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cpu_clken <= '0';
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end if;
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-- clock the Busmon out of phase with the cpu
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-- exactly which cycle is not critical
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if (clk_div = "0111") then
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busmon_clken <= '1';
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else
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busmon_clken <= '0';
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end if;
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-- toggle Phi1/2 on cycles 0 and 8
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if (clk_div = "0000") then
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Phi1 <= '1';
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Phi2 <= '0';
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elsif (clk_div = "1000") then
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Phi1 <= '0';
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Phi2 <= '1';
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end if;
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-- Skew address by one cycle wrt Phi1/2
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-- and hold for a complete cycle
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if (clk_div = "0001") then
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Addr1 <= Addr0;
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R_W_n1 <= R_W_n0;
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Sync1 <= Sync0;
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end if;
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-- Skew data release by one cycle wrt Phi1/2
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if (clk_div = "1000") then
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cpu_dataen <= '1';
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Dout1 <= Dout0;
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elsif (clk_div = "0001") then
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cpu_dataen <= '0';
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Dout1 <= (others => '1');
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end if;
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end if;
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end process;
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-- This reset the DCM if is seems to have stopped outputting a clock
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process(clock49)
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begin
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if rising_edge(clock49) then
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edge0 <= clk_div(0);
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edge1 <= edge0;
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-- Look for an edge on the clock
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if (edge0 /= edge1) then
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dcm_count <= (others => '0');
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elsif (dcm_count = "1111001111") then
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dcm_reset <= '0';
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elsif (dcm_count = "1000000000") then
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dcm_reset <= '1';
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dcm_count <= dcm_count + 1;
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else
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dcm_count <= dcm_count + 1;
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end if;
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end if;
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end process;
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end behavioral;
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