mirror of
https://github.com/hoglet67/AtomBusMon.git
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281 lines
9.9 KiB
VHDL
281 lines
9.9 KiB
VHDL
--------------------------------------------------------------------------------
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-- This file is owned and controlled by Xilinx and must be used solely --
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-- for design, simulation, implementation and creation of design files --
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-- limited to Xilinx devices or technologies. Use with non-Xilinx --
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-- devices or technologies is expressly prohibited and immediately --
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-- terminates your license. --
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-- --
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
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-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
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-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
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-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
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-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
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-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
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-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
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-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
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-- PARTICULAR PURPOSE. --
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-- --
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-- Xilinx products are not intended for use in life support appliances, --
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-- devices, or systems. Use in such applications are expressly --
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-- prohibited. --
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-- --
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-- (c) Copyright 1995-2017 Xilinx, Inc. --
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-- All rights reserved. --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file WatchEvents.vhd when simulating
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-- the core, WatchEvents. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- The synthesis directives "translate_off/translate_on" specified
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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LIBRARY XilinxCoreLib;
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-- synthesis translate_on
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ENTITY WatchEvents IS
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PORT (
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clk : IN STD_LOGIC;
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srst : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC
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);
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END WatchEvents;
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ARCHITECTURE WatchEvents_a OF WatchEvents IS
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-- synthesis translate_off
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COMPONENT wrapped_WatchEvents
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PORT (
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clk : IN STD_LOGIC;
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srst : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC
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);
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END COMPONENT;
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-- Configuration specification
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FOR ALL : wrapped_WatchEvents USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
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GENERIC MAP (
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c_add_ngc_constraint => 0,
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c_application_type_axis => 0,
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c_application_type_rach => 0,
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c_application_type_rdch => 0,
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c_application_type_wach => 0,
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c_application_type_wdch => 0,
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c_application_type_wrch => 0,
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c_axi_addr_width => 32,
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c_axi_aruser_width => 1,
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c_axi_awuser_width => 1,
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c_axi_buser_width => 1,
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c_axi_data_width => 64,
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c_axi_id_width => 4,
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c_axi_ruser_width => 1,
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c_axi_type => 0,
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c_axi_wuser_width => 1,
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c_axis_tdata_width => 64,
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c_axis_tdest_width => 4,
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c_axis_tid_width => 8,
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c_axis_tkeep_width => 4,
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c_axis_tstrb_width => 4,
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c_axis_tuser_width => 4,
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c_axis_type => 0,
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c_common_clock => 1,
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c_count_type => 0,
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c_data_count_width => 10,
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c_default_value => "BlankString",
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c_din_width => 72,
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c_din_width_axis => 1,
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c_din_width_rach => 32,
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c_din_width_rdch => 64,
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c_din_width_wach => 32,
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c_din_width_wdch => 64,
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c_din_width_wrch => 2,
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c_dout_rst_val => "0",
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c_dout_width => 72,
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c_enable_rlocs => 0,
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c_enable_rst_sync => 1,
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c_error_injection_type => 0,
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c_error_injection_type_axis => 0,
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c_error_injection_type_rach => 0,
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c_error_injection_type_rdch => 0,
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c_error_injection_type_wach => 0,
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c_error_injection_type_wdch => 0,
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c_error_injection_type_wrch => 0,
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c_family => "spartan6",
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c_full_flags_rst_val => 0,
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c_has_almost_empty => 0,
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c_has_almost_full => 0,
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c_has_axi_aruser => 0,
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c_has_axi_awuser => 0,
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c_has_axi_buser => 0,
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c_has_axi_rd_channel => 0,
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c_has_axi_ruser => 0,
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c_has_axi_wr_channel => 0,
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c_has_axi_wuser => 0,
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c_has_axis_tdata => 0,
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c_has_axis_tdest => 0,
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c_has_axis_tid => 0,
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c_has_axis_tkeep => 0,
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c_has_axis_tlast => 0,
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c_has_axis_tready => 1,
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c_has_axis_tstrb => 0,
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c_has_axis_tuser => 0,
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c_has_backup => 0,
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c_has_data_count => 0,
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c_has_data_counts_axis => 0,
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c_has_data_counts_rach => 0,
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c_has_data_counts_rdch => 0,
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c_has_data_counts_wach => 0,
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c_has_data_counts_wdch => 0,
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c_has_data_counts_wrch => 0,
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c_has_int_clk => 0,
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c_has_master_ce => 0,
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c_has_meminit_file => 0,
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c_has_overflow => 0,
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c_has_prog_flags_axis => 0,
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c_has_prog_flags_rach => 0,
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c_has_prog_flags_rdch => 0,
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c_has_prog_flags_wach => 0,
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c_has_prog_flags_wdch => 0,
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c_has_prog_flags_wrch => 0,
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c_has_rd_data_count => 0,
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c_has_rd_rst => 0,
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c_has_rst => 0,
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c_has_slave_ce => 0,
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c_has_srst => 1,
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c_has_underflow => 0,
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c_has_valid => 0,
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c_has_wr_ack => 0,
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c_has_wr_data_count => 0,
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c_has_wr_rst => 0,
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c_implementation_type => 0,
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c_implementation_type_axis => 1,
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c_implementation_type_rach => 1,
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c_implementation_type_rdch => 1,
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c_implementation_type_wach => 1,
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c_implementation_type_wdch => 1,
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c_implementation_type_wrch => 1,
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c_init_wr_pntr_val => 0,
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c_interface_type => 0,
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c_memory_type => 1,
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c_mif_file_name => "BlankString",
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c_msgon_val => 1,
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c_optimization_mode => 0,
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c_overflow_low => 0,
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c_preload_latency => 0,
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c_preload_regs => 1,
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c_prim_fifo_type => "512x72",
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c_prog_empty_thresh_assert_val => 4,
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c_prog_empty_thresh_assert_val_axis => 1022,
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c_prog_empty_thresh_assert_val_rach => 1022,
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c_prog_empty_thresh_assert_val_rdch => 1022,
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c_prog_empty_thresh_assert_val_wach => 1022,
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c_prog_empty_thresh_assert_val_wdch => 1022,
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c_prog_empty_thresh_assert_val_wrch => 1022,
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c_prog_empty_thresh_negate_val => 5,
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c_prog_empty_type => 0,
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c_prog_empty_type_axis => 0,
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c_prog_empty_type_rach => 0,
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c_prog_empty_type_rdch => 0,
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c_prog_empty_type_wach => 0,
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c_prog_empty_type_wdch => 0,
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c_prog_empty_type_wrch => 0,
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c_prog_full_thresh_assert_val => 511,
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c_prog_full_thresh_assert_val_axis => 1023,
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c_prog_full_thresh_assert_val_rach => 1023,
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c_prog_full_thresh_assert_val_rdch => 1023,
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c_prog_full_thresh_assert_val_wach => 1023,
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c_prog_full_thresh_assert_val_wdch => 1023,
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c_prog_full_thresh_assert_val_wrch => 1023,
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c_prog_full_thresh_negate_val => 510,
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c_prog_full_type => 0,
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c_prog_full_type_axis => 0,
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c_prog_full_type_rach => 0,
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c_prog_full_type_rdch => 0,
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c_prog_full_type_wach => 0,
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c_prog_full_type_wdch => 0,
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c_prog_full_type_wrch => 0,
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c_rach_type => 0,
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c_rd_data_count_width => 10,
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c_rd_depth => 512,
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c_rd_freq => 1,
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c_rd_pntr_width => 9,
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c_rdch_type => 0,
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c_reg_slice_mode_axis => 0,
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c_reg_slice_mode_rach => 0,
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c_reg_slice_mode_rdch => 0,
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c_reg_slice_mode_wach => 0,
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c_reg_slice_mode_wdch => 0,
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c_reg_slice_mode_wrch => 0,
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c_synchronizer_stage => 2,
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c_underflow_low => 0,
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c_use_common_overflow => 0,
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c_use_common_underflow => 0,
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c_use_default_settings => 0,
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c_use_dout_rst => 1,
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c_use_ecc => 0,
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c_use_ecc_axis => 0,
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c_use_ecc_rach => 0,
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c_use_ecc_rdch => 0,
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c_use_ecc_wach => 0,
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c_use_ecc_wdch => 0,
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c_use_ecc_wrch => 0,
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c_use_embedded_reg => 0,
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c_use_fifo16_flags => 0,
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c_use_fwft_data_count => 1,
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c_valid_low => 0,
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c_wach_type => 0,
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c_wdch_type => 0,
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c_wr_ack_low => 0,
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c_wr_data_count_width => 10,
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c_wr_depth => 512,
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c_wr_depth_axis => 1024,
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c_wr_depth_rach => 16,
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c_wr_depth_rdch => 1024,
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c_wr_depth_wach => 16,
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c_wr_depth_wdch => 1024,
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c_wr_depth_wrch => 16,
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c_wr_freq => 1,
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c_wr_pntr_width => 9,
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c_wr_pntr_width_axis => 10,
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c_wr_pntr_width_rach => 4,
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c_wr_pntr_width_rdch => 10,
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c_wr_pntr_width_wach => 4,
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c_wr_pntr_width_wdch => 10,
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c_wr_pntr_width_wrch => 4,
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c_wr_response_latency => 1,
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c_wrch_type => 0
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);
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-- synthesis translate_on
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BEGIN
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-- synthesis translate_off
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U0 : wrapped_WatchEvents
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PORT MAP (
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clk => clk,
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srst => srst,
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din => din,
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wr_en => wr_en,
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rd_en => rd_en,
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dout => dout,
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full => full,
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empty => empty
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);
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-- synthesis translate_on
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END WatchEvents_a;
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