mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-09-27 03:54:45 +00:00
6ac7902449
Change-Id: Ieeb558b5df1a7b3705874468c98a0b72ebb2d505
207 lines
6.2 KiB
VHDL
207 lines
6.2 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (c) 2019 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : Z80CpuMonALS.vhd
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-- /___/ /\ Timestamp : 29/09/2019
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: Z80CpuMon
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--Device: XC6SLX9
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity Z80CpuMonALS is
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generic (
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num_comparators : integer := 8; -- default value for lx9core board
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avr_prog_mem_size : integer := 1024 * 16 -- default value for lx9core board
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);
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port (
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clock : in std_logic;
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-- Z80 Signals
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RESET_n : in std_logic;
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CLK_n : in std_logic;
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WAIT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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MREQ_n : out std_logic;
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IORQ_n : out std_logic;
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RD_n : out std_logic;
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WR_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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Data : inout std_logic_vector(7 downto 0);
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-- Level Shifers Controls
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OEC_n : out std_logic;
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OEA1_n : out std_logic;
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OEA2_n : out std_logic;
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OED_n : out std_logic;
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DIRD : out std_logic;
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- ID/mode inputs
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mode : in std_logic;
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id : in std_logic_vector(3 downto 0);
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- Switches
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sw1 : in std_logic;
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sw2 : in std_logic;
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-- LEDs
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led1 : out std_logic;
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led2 : out std_logic;
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led3 : out std_logic;
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-- Optional OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic;
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-- Optional Debugging signals
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test : out std_logic_vector(9 downto 0)
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);
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end Z80CpuMonALS;
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architecture behavioral of Z80CpuMonALS is
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signal MREQ_n_int : std_logic;
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signal IORQ_n_int : std_logic;
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signal M1_n_int : std_logic;
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signal RD_n_int : std_logic;
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signal WR_n_int : std_logic;
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signal RFSH_n_int : std_logic;
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signal HALT_n_int : std_logic;
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signal BUSAK_n_int : std_logic;
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signal tristate_n : std_logic;
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signal tristate_ad_n: std_logic;
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signal sw_reset_cpu : std_logic;
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signal sw_reset_avr : std_logic;
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signal led_bkpt : std_logic;
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signal led_trig0 : std_logic;
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signal led_trig1 : std_logic;
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signal TState : std_logic_vector(2 downto 0);
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begin
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sw_reset_cpu <= not sw1;
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sw_reset_avr <= not sw2;
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led1 <= led_bkpt;
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led2 <= led_trig0;
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led3 <= led_trig1;
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MREQ_n <= MREQ_n_int;
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IORQ_n <= IORQ_n_int;
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M1_n <= M1_n_int;
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RD_n <= RD_n_int;
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WR_n <= WR_n_int;
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RFSH_n <= RFSH_n_int;
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HALT_n <= HALT_n_int;
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BUSAK_n <= BUSAK_n_int;
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OEC_n <= not tristate_n;
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OEA1_n <= not tristate_ad_n;
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OEA2_n <= not tristate_ad_n;
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OED_n <= not tristate_ad_n;
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wrapper : entity work.Z80CpuMon
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generic map (
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ClkMult => 12,
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ClkDiv => 25,
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ClkPer => 20.000,
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num_comparators => num_comparators,
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avr_prog_mem_size => avr_prog_mem_size
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)
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port map (
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clock => clock,
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-- Z80 Signals
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RESET_n => RESET_n,
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CLK_n => CLK_n,
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WAIT_n => WAIT_n,
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INT_n => INT_n,
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NMI_n => NMI_n,
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BUSRQ_n => BUSRQ_n,
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M1_n => M1_n_int,
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MREQ_n => MREQ_n_int,
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IORQ_n => IORQ_n_int,
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RD_n => RD_n_int,
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WR_n => WR_n_int,
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RFSH_n => RFSH_n_int,
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HALT_n => HALT_n_int,
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BUSAK_n => BUSAK_n_int,
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Addr => Addr,
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Data => Data,
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-- Buffer Control Signals
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DIRD => DIRD,
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tristate_n => tristate_n,
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tristate_ad_n => tristate_ad_n,
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-- Mode jumper, tie low to generate NOPs when paused
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mode => mode,
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-- External trigger inputs
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trig => trig,
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-- Serial Console
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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-- Switches
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sw_reset_cpu => sw_reset_cpu,
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sw_reset_avr => sw_reset_avr,
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-- LEDs
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led_bkpt => led_bkpt,
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led_trig0 => led_trig0,
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led_trig1 => led_trig1,
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-- OHO_DY1 connected to test connector
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk,
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-- Debugging signals
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test1 => open,
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test2 => TState(0),
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test3 => TState(1),
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test4 => TSTate(2)
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);
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-- Test outputs
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test(0) <= M1_n_int;
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test(1) <= RD_n_int;
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test(2) <= WR_n_int;
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test(3) <= MREQ_n_int;
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test(4) <= IORQ_n_int;
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test(5) <= WAIT_n;
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test(6) <= CLK_n;
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test(7) <= TState(2);
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test(8) <= TState(1);
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test(9) <= TState(0);
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end behavioral;
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