mirror of
https://github.com/hoglet67/AtomBusMon.git
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130 lines
3.5 KiB
VHDL
130 lines
3.5 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (c) 2015 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : AtomBusMon.vhd
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-- /___/ /\ Timestamp : 30/05/2015
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: AtomBusMon
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--Device: XC3S250E
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use work.OhoPack.all ;
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entity AtomCpuMon is
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port (
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clock49 : in std_logic;
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-- 6502 Signals
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Rdy : in std_logic;
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Phi0 : in std_logic;
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Phi1 : out std_logic;
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Phi2 : out std_logic;
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IRQ_n : in std_logic;
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NMI_n : in std_logic;
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Sync : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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R_W_n : out std_logic;
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Data : inout std_logic_vector(7 downto 0);
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SO_n : in std_logic;
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Res_n : in std_logic;
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-- GODIL Switches
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sw1 : in std_logic;
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nsw2 : in std_logic;
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-- GODIL LEDs
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led3 : out std_logic;
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led6 : out std_logic;
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led8 : out std_logic;
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-- OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic
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);
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end AtomCpuMon;
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architecture behavioral of AtomCpuMon is
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signal Din : std_logic_vector(7 downto 0);
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signal Dout : std_logic_vector(7 downto 0);
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signal dy_counter : std_logic_vector(31 downto 0);
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signal dy_data : y2d_type ;
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signal R_W_n_int : std_logic;
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signal Addr_int : std_logic_vector(15 downto 0);
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begin
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cpu : entity work.T65 port map (
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mode => "00",
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Abort_n => '1',
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SO_n => SO_n,
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Res_n => Res_n,
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Enable => '1',
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Clk => not Phi0,
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Rdy => Rdy,
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IRQ_n => IRQ_n,
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NMI_n => NMI_n,
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R_W_n => R_W_n_int,
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Sync => Sync,
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A(23 downto 16) => open,
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A(15 downto 0) => Addr_int(15 downto 0),
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DI(7 downto 0) => Din(7 downto 0),
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DO(7 downto 0) => Dout(7 downto 0)
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);
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Addr <= Addr_int;
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R_W_n <= R_W_n_int;
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Phi1 <= not Phi0;
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Phi2 <= Phi0;
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Din <= Data;
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Data <= Dout when R_W_n_int = '0' else (others => 'Z');
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-- OHO DY1 Display for Testing
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inst_oho_dy1 : entity work.Oho_Dy1 port map (
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dy_clock => clock49,
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dy_rst_n => '1',
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dy_data => dy_data,
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dy_update => '1',
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dy_frame => open,
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dy_frameend => open,
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dy_frameend_c => open,
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dy_pwm => "1010",
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dy_counter => dy_counter,
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dy_sclk => tdin,
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dy_ser => tcclk,
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dy_rclk => tmosi
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);
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dy_data(0) <= hex & "0000" & Addr_int(3 downto 0);
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dy_data(1) <= hex & "0000" & Addr_int(7 downto 4);
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dy_data(2) <= hex & "0000" & "00" & (not nsw2) & sw1;
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led3 <= not sw1;
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led6 <= nsw2;
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led8 <= RES_n;
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end behavioral;
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