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261 lines
8.6 KiB
VHDL
Executable File
261 lines
8.6 KiB
VHDL
Executable File
-- ****
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-- T65(b) core. In an effort to merge and maintain bug fixes ....
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--
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--
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-- Ver 300 Bugfixes by ehenciak added
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-- MikeJ March 2005
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-- Latest version from www.fpgaarcade.com (original www.opencores.org)
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--
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-- ****
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--
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-- 6502 compatible microprocessor core
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--
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-- Version : 0245
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--
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t65/
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--
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-- Limitations :
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--
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-- File history :
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--
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-- 0245 : First version
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.T65_Pack.all;
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entity T65_ALU is
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port(
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Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
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Op : in std_logic_vector(3 downto 0);
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BusA : in std_logic_vector(7 downto 0);
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BusB : in std_logic_vector(7 downto 0);
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P_In : in std_logic_vector(7 downto 0);
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P_Out : out std_logic_vector(7 downto 0);
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Q : out std_logic_vector(7 downto 0)
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);
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end T65_ALU;
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architecture rtl of T65_ALU is
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-- AddSub variables (temporary signals)
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signal ADC_Z : std_logic;
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signal ADC_C : std_logic;
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signal ADC_V : std_logic;
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signal ADC_N : std_logic;
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signal ADC_Q : std_logic_vector(7 downto 0);
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signal SBC_Z : std_logic;
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signal SBC_C : std_logic;
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signal SBC_V : std_logic;
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signal SBC_N : std_logic;
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signal SBC_Q : std_logic_vector(7 downto 0);
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begin
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process (P_In, BusA, BusB)
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variable AL : unsigned(6 downto 0);
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variable AH : unsigned(6 downto 0);
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variable C : std_logic;
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begin
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AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
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AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
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-- pragma translate_off
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if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
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if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
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-- pragma translate_on
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if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
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ADC_Z <= '1';
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else
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ADC_Z <= '0';
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end if;
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if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
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AL(6 downto 1) := AL(6 downto 1) + 6;
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end if;
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C := AL(6) or AL(5);
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AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
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ADC_N <= AH(4);
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ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
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-- pragma translate_off
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if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
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-- pragma translate_on
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if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
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AH(6 downto 1) := AH(6 downto 1) + 6;
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end if;
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ADC_C <= AH(6) or AH(5);
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ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
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end process;
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process (Op, P_In, BusA, BusB)
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variable AL : unsigned(6 downto 0);
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variable AH : unsigned(5 downto 0);
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variable C : std_logic;
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begin
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C := P_In(Flag_C) or not Op(0);
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AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
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AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
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-- pragma translate_off
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if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
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if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
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-- pragma translate_on
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if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
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SBC_Z <= '1';
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else
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SBC_Z <= '0';
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end if;
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SBC_C <= not AH(5);
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SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
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SBC_N <= AH(4);
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if P_In(Flag_D) = '1' then
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if AL(5) = '1' then
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AL(5 downto 1) := AL(5 downto 1) - 6;
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end if;
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AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
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if AH(5) = '1' then
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AH(5 downto 1) := AH(5 downto 1) - 6;
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end if;
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end if;
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SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
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end process;
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process (Op, P_In, BusA, BusB,
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ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
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SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
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variable Q_t : std_logic_vector(7 downto 0);
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begin
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-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
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-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
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P_Out <= P_In;
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Q_t := BusA;
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case Op(3 downto 0) is
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when "0000" =>
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-- ORA
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Q_t := BusA or BusB;
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when "0001" =>
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-- AND
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Q_t := BusA and BusB;
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when "0010" =>
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-- EOR
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Q_t := BusA xor BusB;
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when "0011" =>
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-- ADC
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P_Out(Flag_V) <= ADC_V;
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P_Out(Flag_C) <= ADC_C;
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Q_t := ADC_Q;
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when "0101" | "1101" =>
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-- LDA
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when "0110" =>
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-- CMP
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P_Out(Flag_C) <= SBC_C;
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when "0111" =>
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-- SBC
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P_Out(Flag_V) <= SBC_V;
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P_Out(Flag_C) <= SBC_C;
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Q_t := SBC_Q;
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when "1000" =>
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-- ASL
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Q_t := BusA(6 downto 0) & "0";
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P_Out(Flag_C) <= BusA(7);
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when "1001" =>
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-- ROL
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Q_t := BusA(6 downto 0) & P_In(Flag_C);
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P_Out(Flag_C) <= BusA(7);
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when "1010" =>
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-- LSR
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Q_t := "0" & BusA(7 downto 1);
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P_Out(Flag_C) <= BusA(0);
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when "1011" =>
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-- ROR
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Q_t := P_In(Flag_C) & BusA(7 downto 1);
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P_Out(Flag_C) <= BusA(0);
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when "1100" =>
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-- BIT
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P_Out(Flag_V) <= BusB(6);
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when "1110" =>
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-- DEC
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Q_t := std_logic_vector(unsigned(BusA) - 1);
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when "1111" =>
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-- INC
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Q_t := std_logic_vector(unsigned(BusA) + 1);
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when others =>
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end case;
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case Op(3 downto 0) is
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when "0011" =>
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P_Out(Flag_N) <= ADC_N;
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P_Out(Flag_Z) <= ADC_Z;
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when "0110" | "0111" =>
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P_Out(Flag_N) <= SBC_N;
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P_Out(Flag_Z) <= SBC_Z;
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when "0100" =>
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when "1100" =>
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P_Out(Flag_N) <= BusB(7);
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if (BusA and BusB) = "00000000" then
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P_Out(Flag_Z) <= '1';
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else
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P_Out(Flag_Z) <= '0';
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end if;
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when others =>
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P_Out(Flag_N) <= Q_t(7);
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if Q_t = "00000000" then
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P_Out(Flag_Z) <= '1';
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else
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P_Out(Flag_Z) <= '0';
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end if;
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end case;
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Q <= Q_t;
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end process;
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end;
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