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118 lines
4.6 KiB
VHDL
Executable File
118 lines
4.6 KiB
VHDL
Executable File
-- ****
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-- T65(b) core. In an effort to merge and maintain bug fixes ....
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--
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--
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-- Ver 300 Bugfixes by ehenciak added
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-- MikeJ March 2005
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-- Latest version from www.fpgaarcade.com (original www.opencores.org)
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--
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-- ****
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--
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-- 65xx compatible microprocessor core
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--
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-- Version : 0246
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--
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t65/
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--
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-- Limitations :
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--
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-- File history :
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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package T65_Pack is
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constant Flag_C : integer := 0;
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constant Flag_Z : integer := 1;
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constant Flag_I : integer := 2;
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constant Flag_D : integer := 3;
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constant Flag_B : integer := 4;
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constant Flag_1 : integer := 5;
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constant Flag_V : integer := 6;
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constant Flag_N : integer := 7;
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component T65_MCode
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port(
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Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
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IR : in std_logic_vector(7 downto 0);
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MCycle : in std_logic_vector(2 downto 0);
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P : in std_logic_vector(7 downto 0);
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LCycle : out std_logic_vector(2 downto 0);
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ALU_Op : out std_logic_vector(3 downto 0);
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Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
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Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
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Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
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Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
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BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
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BreakAtNA : out std_logic;
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ADAdd : out std_logic;
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AddY : out std_logic;
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PCAdd : out std_logic;
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Inc_S : out std_logic;
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Dec_S : out std_logic;
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LDA : out std_logic;
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LDP : out std_logic;
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LDX : out std_logic;
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LDY : out std_logic;
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LDS : out std_logic;
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LDDI : out std_logic;
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LDALU : out std_logic;
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LDAD : out std_logic;
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LDBAL : out std_logic;
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LDBAH : out std_logic;
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SaveP : out std_logic;
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Write : out std_logic
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);
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end component;
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component T65_ALU
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port(
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Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
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Op : in std_logic_vector(3 downto 0);
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BusA : in std_logic_vector(7 downto 0);
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BusB : in std_logic_vector(7 downto 0);
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P_In : in std_logic_vector(7 downto 0);
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P_Out : out std_logic_vector(7 downto 0);
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Q : out std_logic_vector(7 downto 0)
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);
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end component;
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end;
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