mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-12-22 16:30:06 +00:00
77 lines
5.5 KiB
Plaintext
77 lines
5.5 KiB
Plaintext
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NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
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NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 1
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NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 2
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NET "Addr<13>" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 3
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NET "Addr<14>" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 4
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NET "Addr<15>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 5
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NET "CLK_n" LOC="P22" | IOSTANDARD = LVCMOS33 | PERIOD = 125.00ns ; # Z80 pin 6
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NET "Data<4>" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 7
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NET "Data<3>" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 8
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NET "Data<5>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 9
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NET "Data<6>" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 10
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#NET "VCC" LOC="P40" | IOSTANDARD = LVCMOS33 ; # Z80 pin 11
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NET "Data<2>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 12
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NET "Data<7>" LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 13
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NET "Data<0>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 14
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NET "Data<1>" LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 15
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NET "INT_n" LOC="P54" | IOSTANDARD = LVCMOS33 ; # Z80 pin 16
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NET "NMI_n" LOC="P57" | IOSTANDARD = LVCMOS33 ; # Z80 pin 17
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NET "HALT_n" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 18
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NET "MREQ_n" LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 19
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NET "IORQ_n" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 20
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NET "RD_n" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 21
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NET "WR_n" LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 22
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NET "BUSAK_n" LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 23
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NET "WAIT_n" LOC="P71" | IOSTANDARD = LVCMOS33 ; # Z80 pin 24
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NET "BUSRQ_n" LOC="P86" | IOSTANDARD = LVCMOS33 ; # Z80 pin 25
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NET "RESET_n" LOC="P84" | IOSTANDARD = LVCMOS33 ; # Z80 pin 26
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NET "M1_n" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 27
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NET "RFSH_n" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 28
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#NET "GND" LOC="P79" | IOSTANDARD = LVCMOS33 ; # Z80 pin 29
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NET "Addr<0>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 30
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NET "Addr<1>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 31
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NET "Addr<2>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 32
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NET "Addr<3>" LOC="P3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 33
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NET "Addr<4>" LOC="P2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 34
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NET "Addr<5>" LOC="P4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 35
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NET "Addr<6>" LOC="P5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 36
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NET "Addr<7>" LOC="P90" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 37
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NET "Addr<8>" LOC="P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 38
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NET "Addr<9>" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 39
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NET "Addr<10>" LOC="P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # Z80 pin 40
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NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
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NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
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NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
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NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Left Switch
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NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Right Switch
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# I/O's for test connector
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#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E2
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#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E3
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NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E4
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NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E5
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NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E6
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#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E7
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#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # connector pin E8
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NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
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NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
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NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
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NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
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NET "test1" LOC="P65" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test2" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test3" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test4" LOC="P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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# This input controls whether the idle mode includes M1 cycles
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NET "mode" LOC="P88" | IOSTANDARD = LVCMOS33 | PULLUP;
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