mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-09-27 03:54:45 +00:00
a29aa3015a
Change-Id: I7ab22f8cca51184b94e709336b661b8685d02d0b
167 lines
4.8 KiB
VHDL
167 lines
4.8 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (c) 2019 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : Z80CpuMonALS.vhd
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-- /___/ /\ Timestamp : 29/09/2019
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: Z80CpuMon
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--Device: XC6SLX9
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity Z80CpuMonALS is
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port (
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clock : in std_logic;
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-- Z80 Signals
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RESET_n : in std_logic;
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CLK_n : in std_logic;
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WAIT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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MREQ_n : out std_logic;
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IORQ_n : out std_logic;
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RD_n : out std_logic;
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WR_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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Data : inout std_logic_vector(7 downto 0);
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-- Level Shifers Controls
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OEC_n : out std_logic;
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OEA1_n : out std_logic;
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OEA2_n : out std_logic;
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OED_n : out std_logic;
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DIRD : out std_logic;
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- ID/mode inputs
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mode : in std_logic;
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id : in std_logic_vector(3 downto 0);
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- Switches
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sw1 : in std_logic;
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sw2 : in std_logic;
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-- LEDs
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led1 : out std_logic;
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led2 : out std_logic;
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led3 : out std_logic;
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-- Optional OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic;
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-- Optional Debugging signals
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test1 : out std_logic;
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test2 : out std_logic;
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test3 : out std_logic;
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test4 : out std_logic
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);
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end Z80CpuMonALS;
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architecture behavioral of Z80CpuMonALS is
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signal BUSAK_n_int : std_logic;
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signal WR_n_int : std_logic;
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signal DOE_n : std_logic;
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begin
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BUSAK_n <= BUSAK_n_int;
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WR_n <= WR_n_int;
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OEC_n <= not BUSAK_n_int;
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OEA1_n <= not BUSAK_n_int;
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OEA2_n <= not BUSAK_n_int;
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OED_n <= not BUSAK_n_int;
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DIRD <= DOE_n;
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wrapper : entity work.Z80CpuMon
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generic map (
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UseT80Core => true,
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LEDsActiveHigh => true,
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SW1ActiveHigh => false,
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SW2ActiveHigh => false,
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ClkMult => 8,
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ClkDiv => 25,
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ClkPer => 20.000,
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num_comparators => 4,
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avr_prog_mem_size => 1024 * 16
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)
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port map (
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clock49 => clock,
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-- Z80 Signals
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RESET_n => RESET_n,
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CLK_n => CLK_n,
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WAIT_n => WAIT_n,
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INT_n => INT_n,
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NMI_n => NMI_n,
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BUSRQ_n => BUSRQ_n,
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M1_n => M1_n,
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MREQ_n => MREQ_n,
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IORQ_n => IORQ_n,
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RD_n => RD_n,
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WR_n => WR_n_int,
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RFSH_n => RFSH_n,
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HALT_n => HALT_n,
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BUSAK_n => BUSAK_n_int,
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Addr => Addr,
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Data => Data,
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DOE_n => DOE_n,
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-- External trigger inputs
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trig => trig,
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-- Serial Console
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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-- Switches
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sw1 => sw1,
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sw2 => sw2,
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-- LEDs
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led3 => led2, -- trig 0
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led6 => led3, -- trig 1
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led8 => led1, -- break
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-- OHO_DY1 connected to test connector
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk,
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-- Debugging signals
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test1 => test1,
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test2 => test2,
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test3 => test3,
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test4 => test4
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);
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end behavioral;
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