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b9d6359be4
The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
19 lines
466 B
Makefile
19 lines
466 B
Makefile
# The root directory of the project
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ROOT = ../../..
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# The common directory for makefile includes, etc.
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COMMON = ../../common
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# The project .bit file produced by the Xilinx .xise project
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PROJECT = AtomCpuMon
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# The target .bit file to be generated including the monitor program
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TARGET = ice6502
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# Frequuency that the AVR runs at
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F_CPU = 19354838
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# Common include files
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include $(COMMON)/Makefile_$(TARGET).inc
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include $(COMMON)/Makefile.inc
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