mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2025-02-03 05:30:46 +00:00
b9d6359be4
The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
77 lines
5.3 KiB
Plaintext
77 lines
5.3 KiB
Plaintext
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NET "CLK_n" TNM_NET = clk_period_grp_clk_n;
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TIMESPEC TS_clk_period_clk_n = PERIOD "clk_period_grp_clk_n" 250ns LOW;
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NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "clock49" LOC="P21" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
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NET "Addr<11>" LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
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NET "Addr<12>" LOC="P29" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
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NET "Addr<13>" LOC="P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
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NET "Addr<14>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4
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NET "Addr<15>" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5
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NET "CLK_n" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 6
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NET "Data<4>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 7
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NET "Data<3>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 8
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NET "Data<5>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 9
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NET "Data<6>" LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 10
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#NET "VCC" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 11
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NET "Data<2>" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 12
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NET "Data<7>" LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 13
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NET "Data<0>" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 14
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NET "Data<1>" LOC="P55" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 15
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NET "INT_n" LOC="P56" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 16
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NET "NMI_n" LOC="P62" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 17
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NET "HALT_n" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 18
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NET "MREQ_n" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 19
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NET "IORQ_n" LOC="P74" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 20
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NET "RD_n" LOC="P75" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 21
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NET "WR_n" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 22
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NET "BUSAK_n" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 23
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NET "WAIT_n" LOC="P80" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 24
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NET "BUSRQ_n" LOC="P81" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 25
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NET "RESET_n" LOC="P82" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 26
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NET "M1_n" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 27
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NET "RFSH_n" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 28
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#NET "GND" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 29
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NET "Addr<0>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 30
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NET "Addr<1>" LOC="P87" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 31
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NET "Addr<2>" LOC="P88" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32
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NET "Addr<3>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 33
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NET "Addr<4>" LOC="P93" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34
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NET "Addr<5>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 35
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NET "Addr<6>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 36
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NET "Addr<7>" LOC="P97" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37
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NET "Addr<8>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 38
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NET "Addr<9>" LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39
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NET "Addr<10>" LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 40
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# LEDs and Switches
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NET "led3" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active
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NET "led6" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active
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NET "led8" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint
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NET "sw1" LOC="P133" | IOSTANDARD = LVCMOS33 ; # reset
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NET "sw2" LOC="P132" | IOSTANDARD = LVCMOS33 ; # interrupt
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# 7-segment LED
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NET tmosi LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET tdin LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET tcclk LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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# UART
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NET "avr_TxD" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "avr_RxD" LOC="P23" | IOSTANDARD = LVCMOS33 ;
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# External trigger inputs
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NET "trig<0>" LOC="P134" | IOSTANDARD = LVCMOS33 ;
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NET "trig<1>" LOC="P137" | IOSTANDARD = LVCMOS33 ;
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# Test outputs
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NET "test1" LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test2" LOC="P45" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test3" LOC="P47" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test4" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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#NET "test5" LOC="P59" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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