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https://github.com/hoglet67/AtomBusMon.git
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b9d6359be4
The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
42 lines
972 B
Plaintext
42 lines
972 B
Plaintext
ADDRESS_MAP avrmap PPC405 0
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ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
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BUS_BLOCK
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mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
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END_BUS_BLOCK;
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BUS_BLOCK
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mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
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END_BUS_BLOCK;
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BUS_BLOCK
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mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
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END_BUS_BLOCK;
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BUS_BLOCK
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mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
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END_BUS_BLOCK;
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BUS_BLOCK
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mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
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END_BUS_BLOCK;
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BUS_BLOCK
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mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
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END_BUS_BLOCK;
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BUS_BLOCK
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mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
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END_BUS_BLOCK;
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BUS_BLOCK
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mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
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END_BUS_BLOCK;
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BUS_BLOCK
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mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
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END_BUS_BLOCK;
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END_ADDRESS_SPACE;
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END_ADDRESS_MAP; |