David Banks 29438683b2 Z80: seperate top level for GODIL and old LX9
Change-Id: I1f339996037bb8a20afb7664877e0ed1d53d3868
2019-11-02 14:50:43 +00:00

19 lines
467 B
Makefile

# The root directory of the project
ROOT = ../../..
# The common directory for makefile includes, etc.
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
PROJECT = Z80CpuMonLX9
# The target .bit file to be generated including the monitor program
TARGET = icez80
# Frequuency that the AVR runs at
F_CPU = 16000000
# Common include files
include $(COMMON)/Makefile_$(TARGET).inc
include $(COMMON)/Makefile.inc