mirror of
https://github.com/hoglet67/AtomBusMon.git
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387 lines
13 KiB
VHDL
387 lines
13 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (c) 2015 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : Z80CpuMon.vhd
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-- /___/ /\ Timestamp : 22/06/2015
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: Z80CpuMon
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--Device: XC3S250E
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use work.OhoPack.all ;
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entity Z80CpuMon is
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generic (
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UseT80Core : boolean := true
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);
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port (
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clock49 : in std_logic;
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-- Z80 Signals
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RESET_n : in std_logic;
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CLK_n : in std_logic;
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WAIT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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MREQ_n : out std_logic;
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IORQ_n : out std_logic;
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RD_n : out std_logic;
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WR_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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Data : inout std_logic_vector(7 downto 0);
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- GODIL Switches
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sw1 : in std_logic;
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nsw2 : in std_logic;
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-- GODIL LEDs
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led3 : out std_logic;
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led6 : out std_logic;
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led8 : out std_logic;
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-- OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic;
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-- Debugging signals
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test1 : out std_logic;
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test2 : out std_logic;
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test3 : out std_logic;
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test4 : out std_logic
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);
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end Z80CpuMon;
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architecture behavioral of Z80CpuMon is
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type state_type is (idle, rd_init, rd_setup, rd, rd_hold, wr_init, wr_setup, wr, wr_hold, release);
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signal state : state_type;
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signal RESET_n_int : std_logic;
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signal cpu_clk : std_logic;
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signal busmon_clk : std_logic;
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signal Addr_int : std_logic_vector(15 downto 0);
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signal RD_n_int : std_logic;
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signal WR_n_int : std_logic;
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signal MREQ_n_int : std_logic;
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signal IORQ_n_int : std_logic;
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signal M1_n_int : std_logic;
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signal WAIT_n_int : std_logic;
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signal TState : std_logic_vector(2 downto 0);
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signal SS_Single : std_logic;
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signal SS_Step : std_logic;
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signal SS_Step_held : std_logic;
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signal CountCycle : std_logic;
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signal skipNextOpcode : std_logic;
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signal Regs : std_logic_vector(255 downto 0);
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signal io_not_mem : std_logic;
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signal io_rd : std_logic;
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signal io_wr : std_logic;
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signal memory_rd : std_logic;
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signal memory_wr : std_logic;
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signal memory_addr : std_logic_vector(15 downto 0);
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signal memory_dout : std_logic_vector(7 downto 0);
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signal memory_din : std_logic_vector(7 downto 0);
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signal memory_done : std_logic;
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signal INT_n_sync : std_logic;
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signal NMI_n_sync : std_logic;
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signal Rdy : std_logic;
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signal Read_n : std_logic;
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signal Read_n0 : std_logic;
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signal Read_n1 : std_logic;
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signal Write_n : std_logic;
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signal Write_n0 : std_logic;
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signal ReadIO_n : std_logic;
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signal ReadIO_n0 : std_logic;
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signal ReadIO_n1 : std_logic;
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signal WriteIO_n : std_logic;
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signal WriteIO_n0 : std_logic;
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signal Sync : std_logic;
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signal Sync0 : std_logic;
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signal Mem_IO_n : std_logic;
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signal nRST : std_logic;
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signal MemState : std_logic_vector(2 downto 0);
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signal Din : std_logic_vector(7 downto 0);
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signal Dout : std_logic_vector(7 downto 0);
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signal Den : std_logic;
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signal ex_data : std_logic_vector(7 downto 0);
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signal rd_data : std_logic_vector(7 downto 0);
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signal mon_data : std_logic_vector(7 downto 0);
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begin
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mon : entity work.BusMonCore
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generic map (
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num_comparators => 4
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)
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port map (
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clock49 => clock49,
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Addr => Addr_int,
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Data => mon_data,
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Phi2 => busmon_clk,
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Rd_n => Read_n,
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Wr_n => Write_n,
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RdIO_n => ReadIO_n,
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WrIO_n => WriteIO_n,
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Sync => Sync,
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Rdy => Rdy,
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nRSTin => RESET_n_int,
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nRSTout => nRST,
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CountCycle => CountCycle,
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trig => trig,
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lcd_rs => open,
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lcd_rw => open,
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lcd_e => open,
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lcd_db => open,
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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sw1 => '0',
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nsw2 => nsw2,
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led3 => led3,
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led6 => led6,
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led8 => led8,
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk,
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Regs => Regs,
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RdMemOut => memory_rd,
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WrMemOut => memory_wr,
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RdIOOut => io_rd,
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WrIOOut => io_wr,
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AddrOut => memory_addr,
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DataOut => memory_dout,
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DataIn => memory_din,
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Done => memory_done,
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SS_Single => SS_Single,
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SS_Step => SS_Step
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);
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GenT80Core: if UseT80Core generate
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inst_t80: entity work.T80a port map (
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TS => TState,
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Regs => Regs,
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RESET_n => RESET_n_int,
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CLK_n => cpu_clk,
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WAIT_n => WAIT_n_int,
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INT_n => INT_n_sync,
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NMI_n => NMI_n_sync,
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BUSRQ_n => BUSRQ_n,
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M1_n => M1_n_int,
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MREQ_n => MREQ_n_int,
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IORQ_n => IORQ_n_int,
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RD_n => RD_n_int,
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WR_n => WR_n_int,
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RFSH_n => RFSH_n,
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HALT_n => HALT_n,
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BUSAK_n => BUSAK_n,
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A => Addr_int,
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Din => Din,
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Dout => Dout,
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DEn => Den
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);
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end generate;
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WAIT_n_int <= WAIT_n when SS_Single = '0' else
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WAIT_n and SS_Step_held;
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CountCycle <= '1' when SS_Single = '0' or SS_Step_held = '1' else '0';
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sync_gen : process(CLK_n, RESET_n_int)
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begin
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if RESET_n_int = '0' then
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NMI_n_sync <= '1';
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INT_n_sync <= '1';
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SS_Step_held <= '1';
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elsif rising_edge(CLK_n) then
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NMI_n_sync <= NMI_n;
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INT_n_sync <= INT_n;
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if (Sync0 = '1') then
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-- stop at the end of T1 instruction fetch
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SS_Step_held <= '0';
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elsif (SS_Step = '1') then
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-- start again when the single step command is issues
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SS_Step_held <= '1';
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end if;
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end if;
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end process;
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-- Logic to ignore the second M1 in multi-byte opcodes
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skip_opcode_latch : process(CLK_n)
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begin
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if rising_edge(CLK_n) then
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if (M1_n_int = '0' and WAIT_n_int = '1' and TState = "010") then
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if (skipNextOpcode = '0' and (Data = x"CB" or Data = x"DD" or Data = x"ED" or Data = x"FD")) then
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skipNextOpcode <= '1';
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else
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skipNextOpcode <= '0';
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end if;
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end if;
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end if;
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end process;
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-- For instruction breakpoints, we make the monitoring decision as early as possibe
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-- to allow time to stop the current instruction, which is possible because we don't
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-- really care about the data (it's re-read from memory by the disassembler).
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Sync0 <= '1' when M1_n_int = '0' and TState = "001" and skipNextOpcode = '0' else '0';
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-- For memory reads/write breakpoints we make the monitoring decision in the middle of T2
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-- but only if WAIT_n is '1' so we catch the right data.
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Read_n0 <= not (WAIT_n_int and (not RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
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Write_n0 <= not (WAIT_n_int and (not WR_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
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ReadIO_n0 <= not (WAIT_n_int and (not RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "010" else '1';
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WriteIO_n0 <= not ( ( RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState = "011" else '1';
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-- Hold the monitoring decision so it is valid on the rising edge of the clock
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-- For instruction fetches and writes, the monitor sees these at the start of T3
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-- For reads, the data can arrive in the middle of T3 so delay until end of T3
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watch_gen : process(CLK_n)
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begin
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if falling_edge(CLK_n) then
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Sync <= Sync0;
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Read_n1 <= Read_n0;
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Read_n <= Read_n1;
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Write_n <= Write_n0;
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ReadIO_n1 <= ReadIO_n0;
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ReadIO_n <= ReadIO_n1;
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WriteIO_n <= WriteIO_n0;
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end if;
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end process;
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-- Register the exec/write data on the rising at the end of T2
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ex_data_latch : process(CLK_n)
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begin
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if rising_edge(CLK_n) then
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if (Sync = '1' or Write_n = '0' or WriteIO_n = '0') then
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ex_data <= Data;
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end if;
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end if;
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end process;
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-- Register the read data on the falling edge of clock in the middle of T3
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rd_data_latch : process(CLK_n)
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begin
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if falling_edge(CLK_n) then
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if (Read_n1 = '0' or ReadIO_n1 = '0') then
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rd_data <= Data;
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end if;
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memory_din <= Data;
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end if;
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end process;
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-- Mux the data seen by the bus monitor appropriately
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mon_data <= rd_data when Read_n <= '0' or ReadIO_n = '0' else ex_data;
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-- Memory access
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Addr <= memory_addr when (state /= idle) else Addr_int;
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MREQ_n <= '1' when (state = rd_init or state = wr_init or state = release) else
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'0' when (state /= idle and io_not_mem = '0') else MREQ_n_int;
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IORQ_n <= '1' when (state = rd_init or state = wr_init or state = release) else
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'0' when (state /= idle and io_not_mem = '1') else IORQ_n_int;
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WR_n <= '0' when (state = wr) else
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'1' when (state /= idle) else WR_n_int;
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RD_n <= '0' when (state = rd_setup or state = rd or state = rd_hold) else
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'1' when (state /= idle) else RD_n_int;
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M1_n <= '1' when (state /= idle) else M1_n_int;
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memory_done <= '1' when (state = rd_hold or state = wr_hold) else '0';
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-- TODO: Also need to take account of BUSRQ_n/BUSAK_n
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Data <= memory_dout when state = wr_setup or state = wr or state = wr_hold else
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Dout when state = idle and Den = '1' else
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(others => 'Z');
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Din <= Data;
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-- TODO: Add refresh generation into idle loop
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men_access_machine : process(CLK_n)
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begin
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if (RESET_n = '0') then
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state <= idle;
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elsif falling_edge(CLK_n) then
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case state IS
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when idle =>
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if (memory_wr = '1' or io_wr = '1') then
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state <= wr_init;
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io_not_mem <= io_wr;
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elsif (memory_rd = '1' or io_rd = '1') then
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state <= rd_init;
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io_not_mem <= io_rd;
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end if;
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when rd_init =>
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state <= rd_setup;
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when rd_setup =>
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if (WAIT_n = '1') then
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state <= rd;
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end if;
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when rd =>
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state <= rd_hold;
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when rd_hold =>
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state <= idle;
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when wr_init =>
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state <= wr_setup;
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when wr_setup =>
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if (WAIT_n = '1') then
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state <= wr;
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end if;
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when wr =>
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state <= wr_hold;
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when wr_hold =>
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state <= release;
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when release =>
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state <= idle;
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end case;
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end if;
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end process;
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RESET_n_int <= RESET_n and (not sw1) and nRST;
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test1 <= TState(0);
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test2 <= TState(1);
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test3 <= TState(2);
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test4 <= CLK_n;
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cpu_clk <= CLK_n;
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busmon_clk <= CLK_n;
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end behavioral;
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