2019-09-26 03:16:28 +00:00
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; Vera Memory Access Assembly Language Routines for C02
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; Requires External Routines RESRXY, SETDST, and SETSRC
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; and External Variables TEMP0 and TEMP1
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2019-09-29 01:59:58 +00:00
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;Vera External Registers
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;$9F20 Address LSB
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;$9F21 Address MSB
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;$9F22 Auto-Increment and Address Bank
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;$9F23 Data Port 0
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;$9F24 Data Port 1
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;$9F25 Control Register
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;$9F26 Interrupt Enable
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;$9F27 Interrupt Status
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;asladr() - Shift Vera Address Left`
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;Args: X = Number of Bits to Shift
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;Updates: TEMP0 = Bank
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; TEMP1 = Address LSB
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; TEMP3 = Address MSB
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;Returns: A = Bank
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; Y,X = Address
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ASLADR: ASL TEMP1 ;Shift LSB Left
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ROL TEMP2 ;Rotate Carry Left into MSB
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ROL TEMP0 ;Rotate Carry Left into LSB
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DEX ;Decrement Shift Count
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BNE ASLADR ;and Loop if Not Zero
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2019-11-15 04:56:33 +00:00
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BRA RESREG ;Return Bank, MSB, LSB
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2019-09-29 01:59:58 +00:00
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2019-10-27 18:25:30 +00:00
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;chkadr(opts,addr) - Check Vera Address
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;Args: A = Bank + Auto-Increment
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; Y,X = Address
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;Returns: A = $00 - Address is Invalid
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; $FF - Address is Valid
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CHKADR: AND #$0F ;Isolate Bank
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CMP #$0F ;If Registers
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BEQ GETVRT ; Return True
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CMP #$02 ;Else If <2
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BCS GETVRT ; Return True
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LDA #$0 ;Else Return False
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RTS
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;clrmem(count) - Write Array to Vera Memory
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;Args: A = Number of Bytes to Clear
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;Returns: A,Y = 0
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; X = Current Data Port
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CLRMEM: TAY ;Copy Number of Bytes to Y
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LDA #0 ;Set Write Value to Zero
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;filmem(byte, count) - Fill Vera Memory with Byte
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;Args: A = Byte to Fill Memory With
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; Y = Number of Bytes to Fill
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;Returns: Y = 0
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; X = Current Data Port
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FILMEM LDX $9F25 ;Get Current Data Port
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FILMEL: STA $9F23,X ;Write Byte to Data Port
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DEY ;Decrement Counter
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BNE FILMEL ;If Not Zero Loop
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RTS
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2019-09-26 03:16:28 +00:00
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;getadr() - Get Vera Address
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;Args: A = Bank + Auto-Increment
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; Y,X = Address
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2019-10-27 18:25:30 +00:00
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GETADR: LDX $9F20 ;Read Address LSB
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LDY $9F21 ;Read Address MSB
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LDA $9F22 ;Read Bank & Auto-Increment
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2019-09-26 03:16:28 +00:00
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RTS
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2019-10-27 18:25:30 +00:00
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;getvrb(&addr) - Get Vera Register Bit Status
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;Args: A = Bit Mask
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; Y,X = Address
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;Returns: A = Mode
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; X = Current Data Port
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GETVRB: STA TEMP0 ;Save Bit Mask
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JSR GETVRG ;Read Register
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AND TEMP0 ;Mask Register Bit
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BEQ GETVRX ;If Set
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GETVRT: LDA #$FF ; Return TRUE
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GETVRX: RTS ;Else Return FALSE
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2019-09-29 01:59:58 +00:00
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;getvrg(&addr) - Read Vera Internal Register
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2019-09-26 03:16:28 +00:00
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;Args: Y,X = Address
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;Returns: A = Mode
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; X = Current Data Port
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2019-09-29 01:59:58 +00:00
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GETVRG: LDA #$0F ;Set Bank to Registers
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2019-09-26 03:16:28 +00:00
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;and Execute GETBYT
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;getbyt(&addr);
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;Args: A = Bank
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; Y,X = Address
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;Affects: Y
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;Returns: A = Contents of Memory
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; X = Current Data Port
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GETBYT: JSR SETADR ;Set Vera Address
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LDX $9F25 ;Get Current Data Port
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LDA $9F23,X ;Read LSB from Data Port
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RTS
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;getmem(count, &addr) - Read Array From Vera Memory
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;Args: A = Number of Bytes to Read
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; Y,X = Address of Array to Read Into
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;Requires: setadr()
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;Sets: DSTLO,DSTHI = Address of Array
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; TEMP0 = Number of Bytes to Read
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;Affects: A
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;Returns: Y = Number of Bytes Read
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; X = Current Data Port
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GETMEM: JSR SETDST ;Save Destination Address
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GETMEA: STA TEMP0 ;Save Number of Bytes
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LDY #0 ;Initialize Counter
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LDX $9F25 ;Get Current Data Port
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GETMEL: LDA $9F23,X ;Read Byte from Data Port
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STA (DSTLO),Y ;Store in Memory
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INY ;Increment Counter
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CPY TEMP0 ;If Limit Not Reached
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BNE GETMEL ; Loop
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2019-10-27 18:25:30 +00:00
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TYA ;Return Count
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RTS
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2019-09-26 03:16:28 +00:00
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2019-09-29 01:59:58 +00:00
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;getvri(addr); Read Vera Register Pair
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2019-09-26 03:16:28 +00:00
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;Args: Y,X = Address
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;Returns: A,X = Integer LSB
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; Y = Integer LSB
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2019-09-29 01:59:58 +00:00
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GETVRI: LDA #$0F ;Set Bank to Registers
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2019-09-26 03:16:28 +00:00
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;getint(addr); Read Integer from Vera Memory
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;Args: A = Bank
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; Y,X = Address
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;Returns: A,X = Integer LSB
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; Y = Integer LSB
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GETINT: AND #$0F ;Set Auto-Increment to 1
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ORA #$10
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JSR SETADR ;Set Vera Address
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LDX $9F25 ;Get Current Data Port
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LDA $9F23,X ;Read LSB from Data Port
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LDY $9F23,X ;Read MSB Data Port
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TAX ;Copy LSB to X
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RTS
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2019-10-27 18:25:30 +00:00
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;regadr(addr) - Set Vera Address to Internal Register
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2019-09-26 03:16:28 +00:00
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;Args: Y,X = Register Address
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2019-10-27 18:25:30 +00:00
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;Returns: A = Bank | Auto-Increment
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REGADR: LDA #$0F ;Set Bank and Auto-Increment
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;setadi(bank,addr) - Set Vera Address with Auto-Increment
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;Args: A = Bank
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; Y,X = Address
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SETADI: ORA #$10 ;Set Auto-Increment to 1
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2019-09-26 03:16:28 +00:00
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;setadr(opts,addr) - Set Vera Address
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;Args: A = Bank + Auto-Increment
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; Y,X = Address
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SETADR: STX $9F20 ;Store Address LSB
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STY $9F21 ;Store Address MSB
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STA $9F22 ;Store Bank & Auto-Increment
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RTS
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2019-10-27 18:25:30 +00:00
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;setvrb(bits, &addr) - Set Vera Register Bits
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;Args: A = Bit Pattern
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; Y,X = Address
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;Uses: TEMP0 = Bit Mask
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;Sets: TEMP1 = Bit Pattern
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;Affects: A,Y,X
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SETVRB: STA TEMP1 ;Save Bit Pattern
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JSR GETVRG ;Read Register
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AND TEMP0 ;Mask Result
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ORA TEMP1 ;Set Bits
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2019-11-15 04:56:33 +00:00
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BRA SETBYN ;Write Back to Register
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2019-10-27 18:25:30 +00:00
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2019-09-26 03:16:28 +00:00
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;setreg(addr) - Set Register
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;Args: A = Value to Write
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; Y,X = Address
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;Sets: TEMP0 = Value to Write
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;Returns: A = Value Written
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; X = Current Data Port
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SETREG: STA TEMP0 ;Save Value to Write
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SETREH: LDA #$0F ;Set Bank, Auto-Increment
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;setbyt(addr) - Write Byte to Vera Memory
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;Args: A = Bank
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; Y,X = Address
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;Uses: TEMP0 = Value to Write
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;Returns: A = Value Written
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; X = Current Data Port
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SETBYT: JSR SETADR ;Set Vera Address
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LDA TEMP0 ;Retrieve Value to Write
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2019-10-27 18:25:30 +00:00
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SETBYN: LDX $9F25 ;Get Current Data Port
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2019-09-26 03:16:28 +00:00
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STA $9F23,X ;Write Value to Data Port
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RTS
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;setrei(addr) - Set Vera Register to Integer
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;Args: Y,X = Address
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;Uses: TEMP1,TEMP2 = Integer Value
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;Affects: A,Y
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;Returns: X = Current Data Port
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SETREI: LDA #$0F ;Set Bank to Registers
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;setina(addr) - Write Integer to Vera Address
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;Args: A = Bank
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; Y,X = Address
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;Uses: TEMP1,TEMP2 = Integer Value
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;Affects: A,Y
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;Returns: X = Current Data Port
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SETINA: ORA #$10 ;Set Auto-Increment to 1
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JSR SETADR ;Set Vera Address
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JSR RESRXY ;Restore Integer into Y,X
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;setint(addr) - Write Integer to Vera Memory
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;Args: Y,X = Integer to Write
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;Requires: setadr();
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;Affects: A,Y
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;Returns: X = Current Data Port
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SETINT: TXA ;Copy LSB to Accumlator
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LDX $9F25 ;Get Current Data Port
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STA $9F23,X ;Write to Data Port
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TYA ;Copy MSB to Accumlator
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STA $9F23,X ;Write to Data Port
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RTS
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;setmem(count, &addr) - Write Array to Vera Memory
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;Args: A = Number of Bytes to Write
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; Y,X = Address of Array to Write From
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;Requires: setadr()
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;Sets: SRCLO,SRCHI = Address of Array
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; TEMP0 = Number of Bytes to Write
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2019-10-27 18:25:30 +00:00
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;Returns: A,Y = Number of Bytes Written
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2019-09-26 03:16:28 +00:00
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; X = Current Data Port
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2019-10-27 18:25:30 +00:00
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SETMEM: JSR SETSRC ;Save Source Address
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SETMET: STA TEMP0 ;Save Number of Bytes
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2019-09-27 16:08:31 +00:00
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SETMEA: LDX $9F25 ;Get Current Data Port
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2019-09-26 03:16:28 +00:00
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LDY #0 ;Initialize Counter
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SETMEL: LDA (SRCLO),Y ;Read Byte from Array
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STA $9F23,X ;Write Byte to Data Port
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INY ;Increment Counter
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CPY TEMP0 ;If Limit Not Reached
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BNE SETMEL ; Loop
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2019-10-27 18:25:30 +00:00
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TYA ;Return Count
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2019-09-26 03:16:28 +00:00
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RTS
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