From d09386dd9b97336728f528fc33fd2feee59a0565 Mon Sep 17 00:00:00 2001
From: Curtis F Kaylor <revcurtis@gmail.com>
Date: Wed, 20 Nov 2019 01:25:57 -0500
Subject: [PATCH] Added BBR, BBS, RMB, SMB Instructions to A02 Assembler

---
 a02.c | 39 ++++++++++++++++++++++++++++++---------
 a02.h | 14 ++++++++++++++
 2 files changed, 44 insertions(+), 9 deletions(-)

diff --git a/a02.c b/a02.c
index 274875d..cdc9338 100644
--- a/a02.c
+++ b/a02.c
@@ -439,23 +439,40 @@ int chkmod(int mode) {
 }
 
 /* Assemble Branch Opcode */
-void asmbrn(void) {
+void asmbrn(int setzp) {
   int offset = 0;
+  int ofsadj = (setzp) ? 2 : 3; //Offset Adjustment
   if (debug) printf("Assembling Branch Opcode Token 0x%02X\n", token);
-  zpage = TRUE;
+  zpage = setzp;
   if (isalpha(*linptr) || *linptr =='.') {
     struct sym *target = evlsym();
-    if (target) offset = (target->value - curadr - 2);
+    if (target) offset = (target->value - curadr - ofsadj);
   }
   else if (cpychr('+')) offset = evlopd(0xFF); 
   else if (cpychr('-')) offset = -evlopd(0xFF); 
-  else xerror("Illegal Branch Operand\n", "");
+  else {
+    opval = evlopd(0xFFFF);
+    if (opval < 0) xerror("Illegal Branch Operand\n", "");
+    offset = opval - curadr - 2;
+  }
+  if (debug) printf("Calculated Branch Offset of %d\n", offset);
   if ((offset > 127 || offset < -128) && passno == 2) 
     xerror("Branch Out of Range\n", "");
   if (debug) printf("Branch Offset %d\n", offset);
   opval = offset & 0xFF;
 }
 
+/* Assemble Zero Page, Relative Opcode */
+void asmzpr(void) {
+  int bitno = -1;
+  if (debug) printf("Assembling ZeroPage (Relative) Opcode Token 0x%02X\n", token);
+  if (strlen(mnmnc) < 4) {opmod = evlopd(7) << 4; cpychr(','); skpspc();} //Set Modifier to Bit Position
+  int zpval = evlopd(0xFF); cpychr(','); skpspc();//Get ZeroPage Operand
+  if (zpval < 0) xerror ("Instruction %s requires Multiple Operands\n", mnmnc);
+  if (amode == 0x0004) {zpage = TRUE; opval = zpval;} //RMB, SMB - Zero Page Operand
+  else {asmbrn(FALSE); opval = opval << 8 | zpval;} //BBR, BBS - Combine Operanda
+}
+
 /* Assemble Immediate Mode Instruction */
 void asmimd(void) {
   if (debug) printf("Assembling Immediate Opcode Token 0x%02X\n", token);
@@ -513,8 +530,10 @@ unsigned char fixopc(void) {
 
 /* Ouput Opcode debug Info */
 void dbgopc(void) {
-  if (debug) printf("token=$%02X, opmod=$%02X, Address Mode: ", token, opmod);
-  switch (opmod) {
+  printf("token=$%02X, opmod=$%02X, Address Mode: ", token, opmod);
+  if (amode == 0x1004) puts("ZeroPage, Relative");
+  else if (amode == 0x0004) puts("ZeroPage");
+  else switch (opmod) {
     case 0x00: if (amode == IMPLD) puts("Implied"); else puts("(Indirect,X)"); break;
     case 0x08: if (opval < 0) puts("Accumulator"); else puts("#Immediate"); break;
     case 0x10: puts("(Indirect),Y"); break;
@@ -542,17 +561,19 @@ int asmopc(int dot) {
   if (debug) printf("Assembling Opcode Token 0x%02X, ", token);
   if (debug) printf("Addressing Mode Mask 0x%04X\n", amode);
   skpspc();
-  if (amode == RELTV) asmbrn(); //Branch (Relative) Instruction
+  if (amode == RELTV) asmbrn(TRUE); //Branch (Relative) Instruction
+  else if (amode == 0x0004 || amode == 0x1004) asmzpr(); //Branch (Relative) Instruction
   else if (cpychr('#')) asmimd();  //Assemble Implied Instruction
   else if (cpychr('(')) asmind(); //Assemble Indirect Instruction
   else asmiaz(); //Assemble Implied/Accumulator/Absolute/ZeroPage Instruction
   if (debug) dbgopc();
-  int opcode = fixopc(); 
+  int opcode = fixopc();
   if (debug) printf("Writing OpCode $%02X\n", opcode);
   outbyt(opcode);                         
+  if (debug) printf("Writing %s Operand %d\n", zpgabs[-zpage], opval);
   if (opval >= 0) {
     if (zpage) outbyt(opval); //Byte Operand
-    else outwrd(opval);                              //Word Operand
+    else outwrd(opval);       //Word Operand
   }
   return TRUE;
 }
diff --git a/a02.h b/a02.h
index 77d90f3..4c3e011 100644
--- a/a02.h
+++ b/a02.h
@@ -22,6 +22,8 @@
 #define INDCY 0x0800  //(Indirect),Y
 #define RELTV 0x1000  //Relative
 
+char zpgabs[][] = {"Absolute", "ZeroPage"};
+
 struct amd {int amode; char desc[12];};
 struct amd amdesc[] = {
   {ACMLT, "Accumulator"}, 
@@ -67,6 +69,18 @@ struct opc opclst[] = {
   {"ASL", 0x02, 0x007D}, {"ROL", 0x22, 0x007D}, {"INC", 0xE2, 0x007D}, {"LSR", 0x42, 0x007D},
   {"ROR", 0x62, 0x007D}, {"DEC", 0xC2, 0x007D}, 
 
+  {"RMB0", 0x07, 0x0004}, {"RMB1", 0x17, 0x0004}, {"RMB2", 0x27, 0x0004}, {"RMB3", 0x37, 0x0004}, 
+  {"RMB4", 0x47, 0x0004}, {"RMB5", 0x57, 0x0004}, {"RMB6", 0x67, 0x0004}, {"RMB7", 0x77, 0x0004}, 
+  {"SMB0", 0x87, 0x0004}, {"SMB1", 0x97, 0x0004}, {"SMB2", 0xA7, 0x0004}, {"SMB3", 0xB7, 0x0004}, 
+  {"SMB4", 0xC7, 0x0004}, {"SMB5", 0xD7, 0x0004}, {"SMB6", 0xE7, 0x0004}, {"SMB7", 0xF7, 0x0004}, 
+  {"RMB", 0x07, 0x0004}, {"SMB", 0x87, 0x0004},
+
+  {"BBR0", 0x0F, 0x1004}, {"BBR1", 0x1F, 0x1004}, {"BBR2", 0x2F, 0x1004}, {"BBR3", 0x3F, 0x1004}, 
+  {"BBR4", 0x4F, 0x1004}, {"BBR5", 0x5F, 0x1004}, {"BBR6", 0x6F, 0x1004}, {"BBR7", 0x7F, 0x1004}, 
+  {"BBS0", 0x8F, 0x1004}, {"BBS1", 0x9F, 0x1004}, {"BBS2", 0xAF, 0x1004}, {"BBS3", 0xBF, 0x1004}, 
+  {"BBS4", 0xCF, 0x1004}, {"BBS5", 0xDF, 0x1004}, {"BBS6", 0xEF, 0x1004}, {"BBS7", 0xFF, 0x1004}, 
+  {"BBR", 0x0F, 0x1004}, {"BBS", 0x8F, 0x1004},
+
   {"TRB", 0x10, 0x0024}, {"TSB", 0x00, 0x0024},
   {"CPX", 0xE0, 0x0026}, {"CPY", 0xC0, 0x0026},
   {"LDX", 0xA2, 0x00A6}, {"STX", 0x82, 0x00A6},